Fix some MIPS software interrupt enabling issues

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4067 42af7a65-404d-4744-a932-0658087f49c3

arch/mips/src/mips32/up_irq.c

@@ -83,7 +83,7 @@ irqstate_t irqsave(void)
   status &= ~CP0_STATUS_IM_MASK;   /* Clear all interrupt mask bits */
   status |= CP0_STATUS_IM_SWINTS;  /* Keep S/W interrupts enabled */
   cp0_putstatus(status);           /* Disable interrupts */
-  return ret;                      /* Return status before interrtupts disabled */
+  return ret;                      /* Return status before interrupts disabled */
 }
 
 /****************************************************************************

arch/mips/src/pic32mx/pic32mx-irq.c

@@ -136,16 +136,19 @@ void up_irqinitialize(void)
 
   /* And finally, enable interrupts */
 
-#ifndef CONFIG_SUPPRESS_INTERRUPTS
-
   /* Interrupts are enabled by setting the IE bit in the CP0 status register */
 
   regval = 0;
   asm volatile("ei    %0" : "=r"(regval));
 
+#ifndef CONFIG_SUPPRESS_INTERRUPTS
   /* Then enable all interrupt levels */
 
   irqrestore(CP0_STATUS_IM_ALL);
+#else
+  /* Enable only software interrupts */
+
+  irqrestore(CP0_STATUS_IM_SWINTS);
 #endif
 }
 

include/cxx/cstring

@@ -52,8 +52,10 @@ namespace std
   using ::size_t;
   using ::strchr;
   using ::strdup;
+  using ::strndup;
   using ::strerror;
   using ::strlen;
+  using ::strnlen;
   using ::strcat;
   using ::strncat;
   using ::strcmp;