More logic to use BASEPRI to control interrupts -- still doesn't work
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5547 42af7a65-404d-4744-a932-0658087f49c3
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- ChangeLog 10 additions, 0 deletionsChangeLog
- TODO 1 addition, 22 deletionsTODO
- arch/arm/include/armv7-m/irq.h 13 additions, 8 deletionsarch/arm/include/armv7-m/irq.h
- arch/arm/include/armv7-m/irq_cmnvector.h 5 additions, 1 deletionarch/arm/include/armv7-m/irq_cmnvector.h
- arch/arm/include/armv7-m/irq_lazyfpu.h 5 additions, 1 deletionarch/arm/include/armv7-m/irq_lazyfpu.h
- arch/arm/include/types.h 6 additions, 0 deletionsarch/arm/include/types.h
- arch/arm/src/armv7-m/up_assert.c 6 additions, 1 deletionarch/arm/src/armv7-m/up_assert.c
- arch/arm/src/armv7-m/up_exception.S 10 additions, 1 deletionarch/arm/src/armv7-m/up_exception.S
- arch/arm/src/armv7-m/up_hardfault.c 13 additions, 3 deletionsarch/arm/src/armv7-m/up_hardfault.c
- arch/arm/src/armv7-m/up_initialstate.c 8 additions, 4 deletionsarch/arm/src/armv7-m/up_initialstate.c
- arch/arm/src/armv7-m/up_schedulesigaction.c 17 additions, 1 deletionarch/arm/src/armv7-m/up_schedulesigaction.c
- arch/arm/src/armv7-m/up_sigdeliver.c 9 additions, 1 deletionarch/arm/src/armv7-m/up_sigdeliver.c
- arch/arm/src/kinetis/kinetis_irq.c 1 addition, 2 deletionsarch/arm/src/kinetis/kinetis_irq.c
- arch/arm/src/kinetis/kinetis_vectors.S 9 additions, 0 deletionsarch/arm/src/kinetis/kinetis_vectors.S
- arch/arm/src/lm/lm_irq.c 1 addition, 2 deletionsarch/arm/src/lm/lm_irq.c
- arch/arm/src/lm/lm_vectors.S 9 additions, 0 deletionsarch/arm/src/lm/lm_vectors.S
- arch/arm/src/lpc17xx/lpc17_irq.c 1 addition, 2 deletionsarch/arm/src/lpc17xx/lpc17_irq.c
- arch/arm/src/lpc17xx/lpc17_vectors.S 9 additions, 0 deletionsarch/arm/src/lpc17xx/lpc17_vectors.S
- arch/arm/src/lpc43xx/lpc43_irq.c 1 addition, 2 deletionsarch/arm/src/lpc43xx/lpc43_irq.c
- arch/arm/src/sam3u/sam3u_irq.c 1 addition, 2 deletionsarch/arm/src/sam3u/sam3u_irq.c
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