- Jul 14, 2014
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Gregory Nutt authored
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Gregory Nutt authored
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Gregory Nutt authored
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- Jul 13, 2014
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Gregory Nutt authored
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- Jul 12, 2014
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Gregory Nutt authored
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Gregory Nutt authored
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Gregory Nutt authored
SAMA5 LCDC: Back out the delay kludge. Increase the LCDC input clock from MCK to 2*MCK was sufficient for all timing instbility problems
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Gregory Nutt authored
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Gregory Nutt authored
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Gregory Nutt authored
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Gregory Nutt authored
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- Jul 11, 2014
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Gregory Nutt authored
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- Jul 10, 2014
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Gregory Nutt authored
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Gregory Nutt authored
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Gregory Nutt authored
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Gregory Nutt authored
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Gregory Nutt authored
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Gregory Nutt authored
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Gregory Nutt authored
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- Jul 09, 2014
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Gregory Nutt authored
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Gregory Nutt authored
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- Jul 08, 2014
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Gregory Nutt authored
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Gregory Nutt authored
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- Jul 07, 2014
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Gregory Nutt authored
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Gregory Nutt authored
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Gregory Nutt authored
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- Jul 06, 2014
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Gregory Nutt authored
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Gregory Nutt authored
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- Jul 05, 2014
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Gregory Nutt authored
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Gregory Nutt authored
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Gregory Nutt authored
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- Jul 03, 2014
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Gregory Nutt authored
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Gregory Nutt authored
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Gregory Nutt authored
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Gregory Nutt authored
SAMA5D3/4: UPLL divisor to generate 48MHz for OHCI is different from the two families. No idea why.
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Gregory Nutt authored
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- Jul 02, 2014
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Gregory Nutt authored
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Gregory Nutt authored
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Gregory Nutt authored
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Gregory Nutt authored
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