- Oct 24, 2013
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Gregory Nutt authored
SAMA5: Add ADC-side of the logic to hook in timer/counter logic needed to drive periodic ADC sampling
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Gregory Nutt authored
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Gregory Nutt authored
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Gregory Nutt authored
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- Oct 23, 2013
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Gregory Nutt authored
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Gregory Nutt authored
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Gregory Nutt authored
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Gregory Nutt authored
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Gregory Nutt authored
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- Oct 22, 2013
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Gregory Nutt authored
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- Oct 21, 2013
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Gregory Nutt authored
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Gregory Nutt authored
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- Oct 20, 2013
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Gregory Nutt authored
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Gregory Nutt authored
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Gregory Nutt authored
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Gregory Nutt authored
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Gregory Nutt authored
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- Oct 19, 2013
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Gregory Nutt authored
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Gregory Nutt authored
SAMA5: Hook RTC into build system; Finish RTC alarm logic; Verify correct behavior of the basic RTC functionality
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Gregory Nutt authored
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- Oct 18, 2013
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Gregory Nutt authored
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Gregory Nutt authored
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Gregory Nutt authored
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Gregory Nutt authored
SAMA5 LCD: Move framebuffers to center of free memory region. That creates a guard band around the framebuffers that gives a little protection from any bad writes into the framebuffer
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Gregory Nutt authored
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Gregory Nutt authored
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Gregory Nutt authored
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Gregory Nutt authored
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- Oct 17, 2013
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Gregory Nutt authored
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- Oct 16, 2013
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Gregory Nutt authored
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- Oct 14, 2013
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Gregory Nutt authored
Misc changes to README files; Update SAMA5D3x-EK NxWM configuration to use Calibration instruction messages
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- Oct 13, 2013
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Gregory Nutt authored
SAMA5 LCDC: Correct how framebuffer memory was being mapped; Remove options to get framebuffer memory in various. Because of the mapping and aligment requirements, those options really cannot be supported
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Gregory Nutt authored
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- Oct 11, 2013
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Gregory Nutt authored
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Gregory Nutt authored
SAMA5 LCDC: Wait when the LCDC is resynchronizing (SIF); Try start-up parameters from Barebox (this still don't work)
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Gregory Nutt authored
SAMA5 LCDC: Default resolution if now RGB565; Add option to select a different output resolution than the sofware resolution (needs to the 24BPP for this LCD).
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- Oct 10, 2013
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Gregory Nutt authored
SAMA5 LCDC: Move DMA descriptors out of internal SRAM and into SDRAM. I am not completely clear, but it looks like the LCDC cannot support DMA from internal SRAM
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Gregory Nutt authored
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Gregory Nutt authored
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Gregory Nutt authored
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