Serial FIONREAD, FIONWRITE, and TERMIOS I/O processing from Mike Smith, Andrew Tridgell, and and Lorenz Meier

MMC/SD SDIO:  Correct return values when multiple block transfers are suppressed.  From Andrew Tridgell via Lorenz Meier

Extend the virtual-to-physical address conversion logic to handle NFS SRM, UDPH SRAM, and external SRAM and PSRAM.

SAMA5: Use RDR/TDR registers for DMA, not FIFO registers; change DMA bit settings to match Atmel example.  Still no DMA

SAMA5 DMA: Need to flush caches; DMA channel depends upon direction of DMA; the maximum transfer size in bytes depends on the number of bytes per transfer

SAMA5: Add PIO interrupt support.  Massive name changes for consistency in PIO vs GPIO naming.  SAMA5D3x-EK:  Add support for SD card detection PIO interrupts

SAMA5:  SPI Driver + AT25 FLASH work; SAM3/4:  Correct an error, SPI will not be correctly configured if CONFIG_SPI_OWNBUS=n

Standard configuration variables used to enable interupt controller debug; SAMA5: Correct handling of spurious interrupts

ARMv7-A:  Map all of .text, .bss, .data., stacks before enabling the MMU and caching. This is simpler and avoids fears I have about caching

ARMv7-A:  Separate CONFIG_PAGING start-up logic into a different startup file.  Too much conditional compilation.