- May 28, 2016
-
-
Gregory Nutt authored
-
Gregory Nutt authored
-
- May 27, 2016
-
-
Gregory Nutt authored
-
Gregory Nutt authored
Add support for SPI 4 and 5 on stm32f411 chips
-
Konstantin Berezenko authored
-
Gregory Nutt authored
-
Gregory Nutt authored
Stefan Kolb's change to the SAMV7 Oneshot Timer (commit d44ecbcf) should also be applied to the SAMA5 oneshot time since the drivers are identical. Here are the commit commits from Stefan's original change: "This is a fix to a problem in the handling of the oneshot timer. Due to a wrong assumption concerning the behavior directly after the start of the timer/counter the function sam_oneshot_cancel(…) calculates the wrong remaining time. The code assumes that the counter register is zero directly after the start of the timer, but this is not true. To start the time/counter a software trigger is invoked, this trigger starts the timer/count and sets the counter register to zero, but the reset of the counter register is not performed instantly. According to the datasheet: “The counter can be reset by a trigger. In this case, the counter value passes to zero on the next valid edge of the selected clock.” Thus the counter is set to zero between 0 and USEC_PER_TICK microseconds after the clock was started. "In my fix I use the freerun count value to determine if at least one tick passed since the start of the timer and thus if the value of the oneshot counter is correct. I also tried to use the function up_timer_gettime(…) to achieve this but, at least if compiled with no optimization the problem vanishes without using the value of the function, the function call takes too long. "Another problem treated in the fix is that if the oneshot timer/counter is canceled, we only know the remaining time with a precision of USEC_PER_TICK microseconds. This means the calculated remaining time is between 0 and USEC_PER_TICK microseconds too long. To fix this I subtract one tick if the calculated remaining time is greater than one tick and otherwise set the remaining time to zero. By doing so the measured times are much more precise as without it."
-
Stefan Kolb authored
This is a fix to a problem in the handling of the oneshot timer. Due to a wrong assumption concerning the behavior directly after the start of the timer/counter the function sam_oneshot_cancel(…) calculates the wrong remaining time. The code assumes that the counter register is zero directly after the start of the timer, but this is not true. To start the time/counter a software trigger is invoked, this trigger starts the timer/count and sets the counter register to zero, but the reset of the counter register is not performed instantly. According to the datasheet: “The counter can be reset by a trigger. In this case, the counter value passes to zero on the next valid edge of the selected clock.” Thus the counter is set to zero between 0 and USEC_PER_TICK microseconds after the clock was started. In my fix I use the freerun count value to determine if at least one tick passed since the start of the timer and thus if the value of the oneshot counter is correct. I also tried to use the function up_timer_gettime(…) to achieve this but, at least if compiled with no optimization the problem vanishes without using the value of the function, the function call takes too long. Another problem treated in the fix is that if the oneshot timer/counter is canceled, we only know the remaining time with a precision of USEC_PER_TICK microseconds. This means the calculated remaining time is between 0 and USEC_PER_TICK microseconds too long. To fix this I subtract one tick if the calculated remaining time is greater than one tick and otherwise set the remaining time to zero. By doing so the measured times are much more precise as without it.
-
Gregory Nutt authored
-
Pierre-noel Bouteville authored
-
Pierre-noel Bouteville authored
* implement POSIX read.
-
Gregory Nutt authored
EFM32, STM32, TIVA: Allow lower half driver to build if any ADC is selected. Should not depend on CONFIG_ADC.
-
- May 26, 2016
-
-
Gregory Nutt authored
-
Gregory Nutt authored
-
Gregory Nutt authored
-
Gregory Nutt authored
-
Gregory Nutt authored
Silence some warnings
-
Gregory Nutt authored
-
Gregory Nutt authored
-
Gregory Nutt authored
-
Gregory Nutt authored
-
Gregory Nutt authored
-
Paul A. Patience authored
-
Gregory Nutt authored
-
Gregory Nutt authored
-
Gregory Nutt authored
-
Gregory Nutt authored
libuavcan: Forgot to change define
-
Gregory Nutt authored
FS: Add logic to detach a file structure from a file descriptor. This is for use only within the OS. It permits an open file or driver to be used across multiple threads.
-
Paul A. Patience authored
-
Gregory Nutt authored
-
Gregory Nutt authored
lcd/Kconfig, Make.defs: Remove dependency of CONFIG_LCD_NXDRIVER for building non-graphic, SLCD drivers.
-
Gregory Nutt authored
-
- May 25, 2016
-
-
Gregory Nutt authored
get I2C working for STM32L4
-
Gregory Nutt authored
1-wire: Initialization/uninitialization functions are not use MCU-independent up_ naming. Should use STM32-specific stm32_ naming. These are not globally accessible but only accessible from STM32 board logic.
-
ziggurat29 authored
get I2C working. some more work regarding clocking computation is needed, as is some inhertited 'todo's from the basis code. but it does work with the devices tested so far.
-
Gregory Nutt authored
-
Gregory Nutt authored
STM32 CAN: Add support for both RX FIFOs
-
Paul A. Patience authored
-
Gregory Nutt authored
-
Sebastien Lorquet authored
Additional configuration option to enable SST26 driver debug output. Using comming FS debug output generates too much output.
-