SAMA5 free-running timer: Add support for a free-running timer wrapper around the low-level timer/counter logic.

SAMA5 timer/counter: Add support for a one-shot timer wrapper around the low-level timer/counter logic.  This also involved several changes that rippled into the ADC driver (untested).

SAMA5 T/C: Can now handle non-constant BOARD_MCK_FREQUENCY. Also now supports methods to attach user interrupt handlers

Remove os_internal.h it has been replace by several new header files under sched/.  There have been some sneak inclusion paths via os_internal.h, so expect a few compilation errors for some architectures

Change all time conversions.  Yech.  New timer units in microseconds breaks all existing logic that used milliseconds in the conversions.  Something likely got broken doing this, probably because I confused a MSEC2TICK conversion with a TICK2MSEC conversion.  Also, the tickless OS no appears fully functional and passes the OS test on the simulator with no errors

Change CONFIG_MSEC_PER_TICK to CONFIG_USEC_PER_TICK.  This gives more options for system timers in general, but more importantly, let's us realize higher resolution for the case of CONFIG_SCHED_TICKLESS=y -- of course, at the risk of some new interger overvflow problems

Rename up_timerinit() to up_timer_initailize(); Add prototypes for candidate interfaces for the tickless OS; Don't build existing timer initialization logic if CONFIG_SCHED_TICKLESS is defined.

SAMA5 SSC: Verify that the requested bit width is supported.  Correct some alignment tests that depend upon the data bit width.

SAMA5 HSMCI: e-enable TX DMA and verify that DMA writes to the SD card are functional.  They are so now TX DMA is re-enabled in the driver.  This might affect the SAMA5D3 platforms where the TX DMA problem was found.  The SAMA4D3 and 4 use the same HSMCI driver.  Much has change since then and it is not surprising that DMA is now functional.  However, the has not be re-verified on the SAMA5D3 which has a different DMA controller.

SAMA5D HSMCI: Fix a problem on card insertion/removal callback handling.  Interrupts were being disable so that the callbacks occurred with interrupts disabled.  This resulted in loss of some interrupts and some not-so-good behaviors.  The solution is to perform all callbacks on the work thread unconditionally (2014-7-29).

SAMA5D HSMCI: Add method to do RX transfer without DMA.  The 8-byte SCR transfer was failing silently with the DMA transfer, leaving the SD card in single bit mode

Change naming from cp_XYZ_cache() to arch_XYP_cache() so that all cache operations will pick up L2 support if it is enabled

 New cache.h file.  Renames cp15_XYZ_cache() to arch_XYZ_cache() and addes L2 cache support if L2 cache is enabled