SAMA5: EHCI now handles low- and full-speed connections by giving them to OHCI; OHCI now uses the work queue to defer interrupt processing; If both OHCI and EHCI are enabled, EHCI is the master of the UHPHS interrupt

SAMA5/ECHI:  Debug register access, add logic to determine transfer size, fix setting of control bit in token

SAMA5 OHCI:  Re-organize some endpoint list data structures.. Strange things happen when semaphores lie in DMA memory which is occasionally invalidated

SAMA5:  Alternatie clock configuration that yields a perfect 48MHz full speed USB clock and a CPU clock of 384MHz

Clean up some LP17xx and STM32 USB host configuration compilation errors due to the massive changes to the USB host interfaces needed to support the SAMA5