STM32 irqfixes found in build testing

Approved-by: Gregory Nutt

kinetis usb clean up

Approved-by: Gregory Nutt

Kinetis:Bugfixes and coexistence of LPUARTs and UARTs as devices

Approved-by: Gregory Nutt

   Add serial init to centralize UART/LPUART management
   Use kinetis_ not up_ where arch specific
   Defined kinetis_[lp]uart_[early]serialinit to facilitate
    bring up both UARTs and LPUARTs as devices and a console

   Support ordering and merging of serial devices names.

   1) Shifted the clock speed of MK20DX128VLH5 to 48 Mhz to be
      able to uses USB.
   2) Set BOARD_OUTDIV3 to 0 - there is no BOARD_OUTDIV3 on a
      MK20DX128VLH5 or K20DX256VLH7

   3) Added BOARD_SOPT2_PLLFLLSEL and BOARD_SOPT2_FREQ along with
      settings for BOARD_SIM_CLKDIV2_USBFRAC and
      BOARD_SIM_CLKDIV2_USBDIV base on the BOARD_SOPT2_FREQ.

  1) Removed SIM_CLKDIV2[USBFRAC, USBDIV] setting as it is now
     done in kinetis_clockconfig
  2) Use BOARD_USB_CLKSRC to select the clock source to the
     USB block
  3) Removed warning
  4) Removed CONFIG_TEENSY_3X_OVERCLOCK from the driver as
     the board.h will now provide BOARD_SIM_CLKDIV2_USBDIV
     and BOARD_SIM_CLKDIV2_USBFRAC to the kinetis_clockconfig

  If a board.h provides BOARD_SIM_CLKDIV2_FREQ it will configure the
  SIM_CLKDIV2 based on the additional provided
  BOARD_SIM_CLKDIV2_USBFRAC and BOARD_SIM_CLKDIV2_USBDIV

  The reason for doing this globaly is that the output the
  SIM_CLKDIV2 divisor may be also used for other IP blocks in
  future configurations (as is done for SIM_CLKDIV3)