Change naming from cp_XYZ_cache() to arch_XYP_cache() so that all cache operations will pick up L2 support if it is enabled

 New cache.h file.  Renames cp15_XYZ_cache() to arch_XYZ_cache() and addes L2 cache support if L2 cache is enabled

 Rename ARMv7-A cache.h to cp15_cache.h.  Things will be broken on this commit until I get the new cache.h in place.

arch/arm/src/armv7-a/arm_l2cc_pl310.c, l2cc.h, l2cc_pl310.h, Kconfig:  Add initiali support for the ARM L2CC-PL310 L2 cache.

rch/arm/armv7-a/l2cc_pl310.h:  Move arch/arm/sama5/chip/sam_l2cc.h to arch/arm/armv7-a/l2cc_pl310.h.  Adjust the two corresponding Kconfig files as well.

LPC17 Ethernet: Added option to use the kernel worker thread to do most of the workload with CONFIG_NET_WORKER_THREAD option in Kconfig.  Eliminated a problem with PHY DP83848C : it doesn't need a specific initialization on mbed. Critical bufix: From time to time (after some hours) the Ethernet receiver would lose one receive interrupt and the IP stack never recover because there is no receive watchdog as the transmit watchdog.  From Max

 Correct the initial value of the BASEPRI register.  This was apparently never being initialized.  From Max

STM32 OTGFS device:  Various changes to try to reduce that amount of time in interrupts handles and with interrupts disbled.  Needs verification on other platforms.  From Petteri Aimonen

SAMA5 HSMCI: Correct multi-block DMA setup; Fixes related to DMA timeout.  Still problems with HSMCI DMA via XDMAC

SAMA4D5 HSMCI: Set burst size to 1, sample DMA registers on timeout, and don't return from transfer until BOTH the HSMCI transfer and DMA complete

SAMA5 LCDC: Back out the delay kludge.  Increase the LCDC input clock from MCK to 2*MCK was sufficient for all timing instbility problems