XTensa: Add an initial implementation of up_initialstate.  Need to think through co-processor support.

Add support for the RISC-V architecture and configs/nr5m100-nexys4 board.  I will be making the FPGA code for this available soon (within a week I would say).  The board support on this is pretty thin, but it seems like maybe a good idea to get the base RISC-V stuff in since there are people interested in it.

Xtensa: Keep task state in TCB (unless you want to redesign signal handling).  Lots of cosmetic clean-up.

Fixes sscan %sn where strlen(data) < n - Indenting removed!

Fixes sscan %sn where strlen(data) < n

F4 Support oversampling by 8