STM32F7:SDMMC, DMA dcache check in stm32_dmacapable and  SDMMC stm32_dma{recv|send}setup

Approved-by: Gregory Nutt <gnutt@nuttx.org>

   In the where CONFIG_SDIO_PREFLIGHT is not used and
   dcache write-buffed mode is used (not write-through)
   buffer alignment is required for DMA transfers because
   a) arch_invalidate_dcache could lose buffered writes data
   and b) arch_flush_dcache could corrupt adjacent memory if
   the buffer and the bufflen, are not on ARMV7M_DCACHE_LINESIZE
   boundaries.

   There is no documantation for the STM32F7 that limits DMA on
   1 bit vrs 4 bit mode.

   In the case dcache write-buffed mode is used (not write-through)
   buffer alignment is required for DMA transfers because
   a) arch_invalidate_dcache could lose buffered writes data
   and b) arch_flush_dcache could corrupt adjacent memory if
   the maddr and the mend+1, the next next address are not on
   ARMV7M_DCACHE_LINESIZE boundaries.

   Updated comment to proper refernce manual for STM32F7 not
   STM32F4.

   Added stm32_dmacapable input paramaters documentation.

stm32f7:rtc Missing semicolon

Approved-by: Gregory Nutt <gnutt@nuttx.org>

STM32L4 DAC: port from STM32.  Note that this does not address the somewhat confusing relation between STM32L4_NDACS and DAC2 config macros that comes from original STM32 code.

readme: more typo fixes

Approved-by: Gregory Nutt <gnutt@nuttx.org>

fix ESP32 gpio enable reg and default UART pin.

Approved-by: Gregory Nutt <gnutt@nuttx.org>

STM32F7: Some STM32F7 builds failed in build testing due to undefined STM32_SRAM1_BASE.  I think that is because stm32_allocateheap.c was not including chip/stm32_memorymap.h