Tiva: Updated files to allow for ADC triggering by the timer. I’ve cleaned up some parts of the ADC code, too, and fleshed out the PWM triggering ioctl.  From Calvin Maguranis

Break out a new internal interface, stm32_rtc_setdatetime().  This eliminates some un-necessary time conversions.  From Freddie Chopin.

Add a skeleton implementation of the RTC lower half interface at arch/arm/src/stm32/stm32_rtc_lowerhalf.c.  This is just the framework for the RTC lower half.  None of the interface methods have yet been implemetned.

LPC17xx:  Add IPv6 support to the LPC17 Ethernet driver.  Untested... I no longer have a proper environment for LPC17 debug.

SAM4 Ethernet Driver:  No supports operation using the high priority work queue so that packet processing can occur outside of interrupt level processing.

SAM4E-EK: The nsh configuration now configures the Ethernet driver for execution on the HP work thread.

Big, very risky change:  Remove all occurrences of up_maskack_irq() that disable and enable interrupts with up_ack_irq() that only acknowledges the interrupts.  This is only used in interrupt decoding logic.  Also remove the logic that unconditionally re-enables interrupts with the interrupt exits.  This interferes with the drivers ability to control the interrupt state.  This is a necessary, sweeping, global change and unfortunately impossible to test.

SAMA5D Ethernet:  Add support for CONFIG_NET_NOTINTS so that the driver can operate from the work queue thread instead of doing everything from the interrupt level.

ARMv7-A interrupt handler:  Should not automatically re-enable interrupts on interrupt return.  That interferes with the driver's ability to manage interrupts.

Add logic so that STM32 Ethernet drivier can avoid interrupt level processing and, instead, execute on the work thread.

SYSLOG: Add an option to use the syslog'ing device as the system consolution.  This option enables a low-level, write-only console device at /dev/console (similar to the low-level UART console device).  From Pierre-noel Bouteville.

STM32 SPI:  The source clock for SPI 4,5, and 6 should be PCLK2, not PCLK1 (for F411, F427, and F429).  Per David Sidrane.