Rename up_timerinit() to up_timer_initailize(); Add prototypes for candidate interfaces for the tickless OS; Don't build existing timer initialization logic if CONFIG_SCHED_TICKLESS is defined.

SAMA5 SSC: Verify that the requested bit width is supported.  Correct some alignment tests that depend upon the data bit width.

SAMA5 HSMCI: e-enable TX DMA and verify that DMA writes to the SD card are functional.  They are so now TX DMA is re-enabled in the driver.  This might affect the SAMA5D3 platforms where the TX DMA problem was found.  The SAMA4D3 and 4 use the same HSMCI driver.  Much has change since then and it is not surprising that DMA is now functional.  However, the has not be re-verified on the SAMA5D3 which has a different DMA controller.

SAMA5D HSMCI: Fix a problem on card insertion/removal callback handling.  Interrupts were being disable so that the callbacks occurred with interrupts disabled.  This resulted in loss of some interrupts and some not-so-good behaviors.  The solution is to perform all callbacks on the work thread unconditionally (2014-7-29).

SAMA5D HSMCI: Add method to do RX transfer without DMA.  The 8-byte SCR transfer was failing silently with the DMA transfer, leaving the SD card in single bit mode

Change naming from cp_XYZ_cache() to arch_XYP_cache() so that all cache operations will pick up L2 support if it is enabled

 New cache.h file.  Renames cp15_XYZ_cache() to arch_XYZ_cache() and addes L2 cache support if L2 cache is enabled

 Rename ARMv7-A cache.h to cp15_cache.h.  Things will be broken on this commit until I get the new cache.h in place.

arch/arm/src/armv7-a/arm_l2cc_pl310.c, l2cc.h, l2cc_pl310.h, Kconfig:  Add initiali support for the ARM L2CC-PL310 L2 cache.

rch/arm/armv7-a/l2cc_pl310.h:  Move arch/arm/sama5/chip/sam_l2cc.h to arch/arm/armv7-a/l2cc_pl310.h.  Adjust the two corresponding Kconfig files as well.

LPC17 Ethernet: Added option to use the kernel worker thread to do most of the workload with CONFIG_NET_WORKER_THREAD option in Kconfig.  Eliminated a problem with PHY DP83848C : it doesn't need a specific initialization on mbed. Critical bufix: From time to time (after some hours) the Ethernet receiver would lose one receive interrupt and the IP stack never recover because there is no receive watchdog as the transmit watchdog.  From Max

 Correct the initial value of the BASEPRI register.  This was apparently never being initialized.  From Max

STM32 OTGFS device:  Various changes to try to reduce that amount of time in interrupts handles and with interrupts disbled.  Needs verification on other platforms.  From Petteri Aimonen