- Sep 01, 2015
-
-
Ilya Averyanov authored
-
- Aug 31, 2015
-
-
Gregory Nutt authored
-
Gregory Nutt authored
SAMV71 QSPI: Fix frequency calculation. Need to use ceil() type logic so that requested frequency is not exceeded
-
Gregory Nutt authored
-
Gregory Nutt authored
-
Gregory Nutt authored
arch/arm/src/up_iternal.h and several ARM Make.defs files: In the original implementation, NOT defined(CONFIG_ARMV7M_CMNVECTOR) was a sufficient test to determine if lazy floating point register saving was being used. But recents changes added common lazy register as well so now that test must be (NOT defined(CONFIG_ARMV7M_CMNVECTOR) || defined(CONFIG_ARMV7M_LAZYFPU)).
-
- Aug 30, 2015
-
-
Gregory Nutt authored
-
- Aug 29, 2015
-
-
Gregory Nutt authored
-
Gregory Nutt authored
-
Gregory Nutt authored
-
- Aug 28, 2015
-
-
Gregory Nutt authored
-
Gregory Nutt authored
-
- Aug 27, 2015
-
-
Gregory Nutt authored
-
Gregory Nutt authored
-
Gregory Nutt authored
-
- Aug 26, 2015
-
-
Gregory Nutt authored
-
- Aug 25, 2015
-
-
Gregory Nutt authored
SAMV71 QSPI: Use new QSPI interface. Can't use SPI interface as planned; the hardware architectue is too different
-
- Aug 24, 2015
-
-
Gregory Nutt authored
-
Gregory Nutt authored
Networking: Move where the local loopback device is initialized from board_app_intiialize() to up_intiialize() so that it will happen automatically
-
Gregory Nutt authored
Upstream_446_clock
-
Gregory Nutt authored
-
Gregory Nutt authored
-
David Sidrane authored
-
David Sidrane authored
-
- Aug 23, 2015
-
-
Gregory Nutt authored
LPC17: Fix RAM vector table alignment for the LPC17 family. The ARMv7-M TRM only requires 128-byte alignment for vector tables; the LPC17, however, requires 256 byte alignment
-
- Aug 22, 2015
-
-
Gregory Nutt authored
-
David Sidrane authored
-
David Sidrane authored
-
Pavel Pisa authored
arch/arm/src/lpc17: Actually implement options to use external SDRAM and or SRAM for the heap. From Pavel Pisa
-
Gregory Nutt authored
-
Gregory Nutt authored
-
Gregory Nutt authored
-
Gregory Nutt authored
Upstream_446
-
- Aug 21, 2015
-
-
David Sidrane authored
-
David Sidrane authored
-
David Sidrane authored
-
David Sidrane authored
-
Gregory Nutt authored
SAMV7 QSPI: Add framework for a QSPI driver. Initial commit is just the SPI driver with some name changes
-
Gregory Nutt authored
SAMV7 USBHS Device: After aligning DMA buffers and disabling write-back data cache, the DCD driver is fully functional using the CDC/ACM device
-
Gregory Nutt authored
All ARMV7-M IRQ setup: Always set the NVIC vector table address. This is needed in cases where the code is running with a bootload and when the code is running from RAM. It is also needed by the logic of up_ramvec_initialize() which gets the vector base address from the NVIC. Suggested by Pavel Pisa
-