SAM3/4 GPIO: Enable peripheral clock for GPIO port when GPIO is configured as input.

The value of a GPIO input is only sampled when the peripheral clock for
the port controller the GPIO resides in is enabled. Therefore we need
to enable the clock even when polling a GPIO.

A consequence of Max's change to the logic to enable access to the backup domain is that every call to enabledbkp(true) must be followed by a matching call to enablebkp(false).  There was one cse in both RTCC drivers where that may not always be true.

SPI3, see datasheet:
www.st.com/resource/en/datasheet/stm32f373cc.pdf

I searched for other members of STM32F37XX family and they also have 3 SPIs:
http://www.st.com/content/st_com/en/search.html#q=STM32F37-t=keywords-page=1

SPI bit order:  Add configuration setting to indicate if an architecture-specif SPI implementation does or does not support LSB bit order.

Add check of return value in drivers affected by last change:  Report the error on a failure to set the bit order.

STM32 and EFM32 SPI drivers adopted an incompatible conventions somewhere along the line.  The set the number of bits to negative when calling SPI_SETBITS which had the magical side-effect of setting LSB first order of bit transmission.  This is not only a hokey way to pass control information but is supported by no other SPI drivers.

This change three things:  (1) It adds HWFEAT_LSBFIRST as a new H/W feature.  (2) It changes the implementations of SPI_SETBITS in the STM32 and EFM32 derivers so that negated bit numbers are simply errors and it adds the SPI_HWFEATURES method that can set the LSB bit order, and (3) It changes all calls with negative number of bits from all drivers: The number of bits is now always positive and SPI_HWFEATUREs is called with HWFEAT_LSBFIRST to set the bit order.

Enable TM4C1294-launchpad board build