Tive Timer:  Add support for ADC trigger generation from one-shot and periodic timers for timeout and match evetns

Tiva Timer: Add support to set the match regiser(s) relative to the timer counter (and prescale) registers.  Enable match interrupts.  These are one time interruprts:  After the match interrupt is dispatched, further match interrupts are disabled

Tive System Control: Add logic to configure the alternatie clock source (ALTCLK).  Needed by the Tiva timer module

STM32 SDIO:  Don't let architectures select CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE unless they have implemented SDIOWAIT_WRCOMPLETE

MMCSD SDIO:  Add support for a new SDWAIT_WRCOMPLETE condition.  The previous logic used a busy-wait loop to pool the card R1 start to determine when the card was ready for the next transfer.  That busy-wait can be quite long -- hundreds of milliseconds.  And alternative is to look the the SD D0 pin which will change state when the card is no longer busy.

This logic implements a change the avoids the busy-wait poll by reconfiguring the SD D0 pin as a GPIO interrupt, then waiting for the card to becom ready without taking up CPU cycles.

This change is conditioned on CONFIG_MMCSD_SDIOWATI_WRCOMPLETE and is currenlty only implemented for the STM32 SDIO driver.

From David Sidrane

TM4C129X Timer:  Add some missing addresses and some of the register bit definitions.  Still incomplete

TM4C129X Timer:  Update addresses in the timer register definitions file.  Still missing bit field definitions

Tiva IRQs:  Fix IRQ control logic; was limited to only 64 IRQs.  That is a problem for higher numbered IRQs on many platforms

Tiva PHY Interrupts: Need to read the PHY interrupt status register in order to clear the pending PHY interrupt

Tiva Ethernet: Removed logic that holds the PHY and re-ordered some reset logic.  Can not ping the DK