SAMA5:  Alternatie clock configuration that yields a perfect 48MHz full speed USB clock and a CPU clock of 384MHz

Clean up some LP17xx and STM32 USB host configuration compilation errors due to the massive changes to the USB host interfaces needed to support the SAMA5

SAMA5:  Major restructuring of the the OHCI driver drivers to better handle the multiple root hub ports and concureent transfers on each port.

Separate wait() and enumerate() methods from struct usbhost_driver_s and move to new interface, struct usbhost_connection_s.  This is part of the necessary restructuring of the USB host interface to support multiple root hub ports.

Add untested OHCI driver for the SAMA5; structure naming and header files for USB host initialization prototypes

Serial FIONREAD, FIONWRITE, and TERMIOS I/O processing from Mike Smith, Andrew Tridgell, and and Lorenz Meier

MMC/SD SDIO:  Correct return values when multiple block transfers are suppressed.  From Andrew Tridgell via Lorenz Meier

Extend the virtual-to-physical address conversion logic to handle NFS SRM, UDPH SRAM, and external SRAM and PSRAM.

SAMA5: Use RDR/TDR registers for DMA, not FIFO registers; change DMA bit settings to match Atmel example.  Still no DMA

SAMA5 DMA: Need to flush caches; DMA channel depends upon direction of DMA; the maximum transfer size in bytes depends on the number of bytes per transfer