Standard configuration variables used to enable interupt controller debug; SAMA5: Correct handling of spurious interrupts

SAMA5: Change mapping of vector tables to work around that fact that I don't understand how the AXI MATRIX remap works

ARMv7-A:  Add cp15_disable_dcache(); SAMA5: nor_main.c no disables MMU and caches; Should not remap ISRAM to address 0x0 unless we booted into ISRAM

SAMA5: The ostest configuration have been converted to run out of NOR flash.  There is more to be done, however

Fix an uninitialized register error that crept into the ARM9 start up code many years ago and was recently cloned into the Cortex-A5.  Obviously no on has used NuttX with ARM9 for years

Revamp the way external memory regions are configured; Add logic to add SAMA5 external memory regions to the heap

SAMA5 clock configuration should now agree with Atmel sample code; Added header file with macros to enable and disable peripheral clocking