Combination of RXDMA + IFLOWCONTROL does not work as one might expect.
Since RXDMA uses circular DMA-buffer, DMA will always keep reading new
data from USART peripheral even if DMA buffer underruns. Thus this
combination only does following: RTS is asserted on USART setup and
deasserted on shutdown and does not perform actual RTS flow-control.

Data loss can be demonstrated by doing long up_mdelay inside irq
critical section and feeding data to RXDMA+IFLOWCONTROL UART.

 STM32F7: default CONFIG_STM32F7_DMACAPABLE to 'n'.  STM32F7 does not have CCM RAM but DTCM, so this option does not need to enabled. DTCM RAM is DMA-able through CPU AHBS bus.

tm32: stm32l15xxx_rcc: configure medium performance voltage range and zero wait-state when allowed by SYSCLK setting

Zero wait-state for flash can be configured when:
 Range 1 and SYSCLK <= 16 Mhz
 Range 2 and SYSCLK <= 8 Mhz
 Range 3 and SYSCLK <= 4.2 Mhz

Medium performance voltage range (1.5V) can be configured when SYSCLK is up to 16 Mhz and PLLVCO up to 48 Mhz.

Fixed gconfig target.

Approved-by: Gregory Nutt <gnutt@nuttx.org>

6loWPAN: Add option to dump buffers.  Fix some issues with calculation of the IEEE802.15.4 header size.

STM32:add I2C3 SDA pin mapping for STM32F411

Approved-by: Gregory Nutt <gnutt@nuttx.org>

wireless/ieee802154: Add initialization logic for loopback driver; configs/sim: Add configuration for testing 6loWPAN; net/sixlowpan: Fix for compilation with debug output enabled.