- Copy net/devif/devif_input.c to ipv6_input.c.  Remove all IPv4-specific logic.
- Rename net/devif/devif_input.c to ipv4_input.c.  Remove all IPv6-specific logic
- Split IPv4 header structure out as net_ipv4hdr_s from net_iphdr_s

Networking:  (1) Copied all ICMP sources files to net/icmpv6 with proper renaming and removal of IPv4 logic, (2) remove IPv6 logic from files in net/icmp, (3) copied include/nuttx/icmp.h to icmpv6.h and removed IPv4 specific logic, (4) removed all IPv6 logic from icmp.h, (5) IP_HDRLEN became IPv4_HDRLEN and IPv6_HDRLEN, (6) ip_chksum() became ipv4_chksum() and ipv6_chksum(), and (7) added partial support for ICMPv6 statistics.

Network: Add an IPv4 configuration option.  Hardcoded to =y for now, but I would like to be able to select IPv4 and/or IPv6 in the future

This is not the official configuration for the PX4 board and has led to confusion by NuttX users.  The board configuration also requires some ongoing maintenance and customization to support ongoing PX4 testing and evaluation.  It is best retained the PX4 repositories where it can be properly maintained and not in the upstream NuttX repository.

Removed setting of the initial timer interval load value (or, rather, it is always set to zero for a free-running timer).  Also, do not unconditional enable the timer out interrupt.  The timerout interrupt is not not enabled until tiva_timer32_setinterval() is called.

Timer Timer:  Timer driver now initializes without complaints.  Need a test driver of some kind to make more testing progress.

Tiva Timer:  Rename tiva_timerlow.c to tiva_timerlow32.c since it only supports 32-bit periodic timers

Tiva Timer:  Allow timeout interrupts even if the reload value is zero.  That is the value that is need to get an interrupt on the wrap from 0xffffffff to 0x00000000

Tiva Timer: Add conditional compilation to enable/disable each timer feature.  Not only does this reduce the footprint by suppressing unused features, it also protects from partially implemented features that are now conditioned on EXPERIMENTAL

Tive Timer:  Add support for ADC trigger generation from one-shot and periodic timers for timeout and match evetns

Tiva Timer: Add support to set the match regiser(s) relative to the timer counter (and prescale) registers.  Enable match interrupts.  These are one time interruprts:  After the match interrupt is dispatched, further match interrupts are disabled

Tive System Control: Add logic to configure the alternatie clock source (ALTCLK).  Needed by the Tiva timer module