- Nov 09, 2016
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Sebastien Lorquet authored
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Sebastien Lorquet authored
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- Nov 08, 2016
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Gregory Nutt authored
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Gregory Nutt authored
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Gregory Nutt authored
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Marc Rechté authored
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Gregory Nutt authored
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- Nov 07, 2016
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Gregory Nutt authored
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Ramtin Amin authored
LM32: Move interrupt definitions from common irq.h to lm32/irq.h. Remove unused misoc_uart.c and .h
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Ramtin Amin authored
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Gregory Nutt authored
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Marc Rechté authored
STM37xx PWM: Add PWM driver support for STMF37xx. The changes have been tested successfuly for TIM4 and TIM17 (different IPs).
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Gregory Nutt authored
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Gregory Nutt authored
STM32F7 SD/MMC driver depends on CONFIG_SDIO_DMA which is only defined in stm32/Kconfig. Changed to CONFIG_STM32F7_SDMMC_DMA and defined in stm32f7/Kconfig.
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Gregory Nutt authored
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Gregory Nutt authored
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Gregory Nutt authored
stm32f7 important usb fixes
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Gregory Nutt authored
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Gregory Nutt authored
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Gregory Nutt authored
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Gregory Nutt authored
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Ramtin Amin authored
LM32: Correct some assembly language interrupt handling issues. Now the basic port seems functional.
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Lok Tep authored
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- Nov 06, 2016
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Gregory Nutt authored
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Gregory Nutt authored
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Gregory Nutt authored
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Gregory Nutt authored
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Gregory Nutt authored
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Gregory Nutt authored
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Gregory Nutt authored
Fix armv7r
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Gregory Nutt authored
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Heesub Shin authored
Signal sent from work_signal() may interrupt the low priority worker thread that is already running. For example, the worker thread that is waiting for a semaphore could be woken up by the signal and break any synchronization assumption as a result. It also does not make any sense to send signal if it is already running and busy. This commit fixes it.
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Heesub Shin authored
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Heesub Shin authored
Thumb flag in CPSR is not restored back when the context switch occurs while executing thumb instruction. Reported-by:
Eunbong Song <eunb.song@samsung.com> Signed-off-by:
Byoungtae Cho <bt.cho@samsung.com> Signed-off-by:
Heesub Shin <heesub.shin@samsung.com>
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Heesub Shin authored
A sporadic hang with consequent crash is observed when booting: arm_prefetchabort: Prefetch abort. PC: 04d34a00 IFAR: 04d34a00 IFSR: 00000008 up_assert: Assertion failed at file:armv7-r/arm_prefetchabort.c line: 87 task: init up_dumpstate: Current sp: 004c3df0 up_dumpstate: Interrupt stack: up_dumpstate: base: 004c05fc up_dumpstate: size: 00000800 up_dumpstate: User stack: up_dumpstate: base: 004c3f58 up_dumpstate: size: 00000fec up_dumpstate: User Stack up_stackdump: 004c3de0: 004a0d14 004c3df0 004c3f58 004a0d20 00000057 004c2c58 09000000 004a42a4 up_stackdump: 004c3e00: 00000003 004c3e10 004a0f1c 004bbcef 33c44b00 004a0f28 04d34a00 00000008 up_stackdump: 004c3e20: 00000008 004a01bc 004bfd38 00000001 00007fff 00000001 34134a00 d83e4c00 up_stackdump: 004c3e40: 09000000 00000000 33c44b00 d83e4c00 0c3f4c00 00000000 00000000 00000003 up_stackdump: 004c3e60: 004c3e70 004a1494 04d34a00 200b0253 004c3ed8 004a5298 004c3ed8 6d00006d up_stackdump: 004c3e80: 0000006d 004bc3f4 00000009 004a4f64 00000009 b9e0784f 333f3ed0 69d4227d up_stackdump: 004c3ea0: d81f09bd 0f867344 5a7e2c12 8acefd34 5d00dc1b 004bc432 004c3f08 004c0e08 up_stackdump: 004c3ec0: 00000000 00000000 00000000 00000000 00000000 004a4210 004a5258 004a5300 up_stackdump: 004c3ee0: 00000000 00000001 ffffffff 004c3f80 000002b0 004a4234 00000007 004c3f08 up_stackdump: 004c3f00: 004a58b4 004bc432 004bc3f4 004c3f80 000002b0 0000029c 00000000 0000029c up_stackdump: 004c3f20: 00000000 004a5900 0000ff01 00000000 00000000 004a61f4 00000000 004a5fa4 up_stackdump: 004c3f40: 00000000 004a5f6c 00000000 004a2668 00000000 00000000 b7509f04 004c3f64 up_registerdump: R0: 00000001 00007fff 00000001 34134a00 d83e4c00 09000000 00000000 33c44b00 up_registerdump: R8: d83e4c00 0c3f4c00 00000000 00000000 00000003 004c3e70 004a1494 04d34a00 up_registerdump: CPSR: 200b0253 It seems to be caused by the corrupted or wrong CPSR restored on return from exception. NuttX restores the context using code like this: msr spsr, r1 GCC translates this to: msr spsr_fc, r1 As a result, not all SPSR fields are updated on exception return. This should be: msr spsr_fsxc, r1 On some evaluation boards, spsr_svc may have totally invalid value at power-on-reset. As it is not initialized at boot, the code above may result in the corruption of cpsr and thus unexpected behavior. Reported-by:
Eunbong Song <eunb.song@samsung.com> Signed-off-by:
Heesub Shin <heesub.shin@samsung.com>
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Heesub Shin authored
s/ARMV7M/ARMV7R/g Reported-by:
Eunbong Song <eunb.song@samsung.com> Signed-off-by:
Heesub Shin <heesub.shin@samsung.com>
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Heesub Shin authored
This commit adds functions for enabling and disabling d/i-caches which were missing for ARMv7-R. Signed-off-by:
Heesub Shin <heesub.shin@samsung.com>
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Heesub Shin authored
Unlike in ARMv7-A/M, Kconfig entries for data and instruction caches are currently missing in ARMv7-R. This commit adds those missing Kconfig entries. Actual implmenetation for those functions will be added in the subsequent patches. Signed-off-by:
Heesub Shin <heesub.shin@samsung.com>
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Heesub Shin authored
mpu_control() is invoking cp15_wrsctlr() around SCTLR update redundantly. Signed-off-by:
Heesub Shin <heesub.shin@samsung.com>
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Heesub Shin authored
In ARMv7-R, [31:5] bits of DRBAR is physical base address and other bits are reserved and SBZ. Thus, there is no point in passing other than the base address. Signed-off-by:
Heesub Shin <heesub.shin@samsung.com>
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