SAMA5 EMAC:  Need to pace RX and TX because and RX can result in a TX; Process TX interrupt events before TX interrupt events for the same reason

SAMA5 EMAC: Add some need D-Cache Flush/Invalidate operations.  Add support for CONFIG_NET_DUMPPACKET

Move CONFIG_NET_DUMPPACKET from LPC17 and STM32 to commong network drivers.  Automatically enabled CONFIG_NETDEVICES when any Ethernet driver is enabled

Move CONFIG_NET_DUMPPACKET from LPC17 and STM32 to commong network drivers.  Automatically enabled CONFIG_NETDEVICES when any Ethernet driver is enabled

SAMA5 UDPHS:  Dont' reject read request submissions while stalled.  That causes an infinite loop.  When stalling, cancel all pending write requests, but cancel only a reqd request if it is in progress.  It will be immediately requeued

SAMA5 OHCI:  Back out a change, the real root cause was a bug in the cache logic so the hack is no longer necessary

SAMA5 OHCI:  Fix some strange Dcache problems that I still don't understand; end address on cache operations is end+1, not end

ARMv7-A: Clarify end address paramet in cache operations:  It is the end+1 address, not the end address

SAMA5 OHCI:  Fix some problems with D-Cache coherency and physical addressing related to interrupt endpoints

SAMA5 OHCI:  When UPLL drives OHCI the logically correct divider of 10 does not work;  But a divider of 5 does.  Why?

SAMA5 EHCI:  Fix bits being clobbered in PORTSC on hand-off to OHCI.  OHCI: Fix some more trace configuration issues.  Both:  Don't muck with SFR port selection bits once they have been initialized

SAMA5 EMAC:  Resolve issues with DUAL PHY support needed for both EMAC and GMAC peripherals.  EMAC driver is now code complete and builds without complaint