LPC17 Ethernet: Added option to use the kernel worker thread to do most of the workload with CONFIG_NET_WORKER_THREAD option in Kconfig.  Eliminated a problem with PHY DP83848C : it doesn't need a specific initialization on mbed. Critical bufix: From time to time (after some hours) the Ethernet receiver would lose one receive interrupt and the IP stack never recover because there is no receive watchdog as the transmit watchdog.  From Max

 Correct the initial value of the BASEPRI register.  This was apparently never being initialized.  From Max

STM32 OTGFS device:  Various changes to try to reduce that amount of time in interrupts handles and with interrupts disbled.  Needs verification on other platforms.  From Petteri Aimonen

SAMA5 HSMCI: Correct multi-block DMA setup; Fixes related to DMA timeout.  Still problems with HSMCI DMA via XDMAC

SAMA4D5 HSMCI: Set burst size to 1, sample DMA registers on timeout, and don't return from transfer until BOTH the HSMCI transfer and DMA complete

SAMA5 LCDC: Back out the delay kludge.  Increase the LCDC input clock from MCK to 2*MCK was sufficient for all timing instbility problems

SAMA5 PIO: Fix a typo in Schmitt trigger configuration; Configure pin as a a vanilla input first so that final pin configuration is more read-able (i.e., easier to debug)

SAMA5 TWI: Some restructured needed by up_i2creset.  Also timeout needs to vary with the size of the transfer and if debug is on or not

Use sam_pio_forceclk() so that we can read the current state of an open-drain output in the TWI reset logic.

Add a new interface sam_pio_forceclk() that can be used to force PIO clocking on.  I am afraid I was too conservative with PIO clocking in the initial design; this is the price

SAMA5D3/4 HEAP: Add a configuration option to reserve DRAM for a framebuffer when executing out of DRAM.