Fix major misthink in Cortex-M0 port:  The Cortex-M0 has no BASEPRI register.  We have to revert to using the nasty PRIMASK register

Fixes to the LM4F clock configuration.  Errors in register handling caused everything to run at half speed

LPC17xx GPIO interrupt fixes: lpc17_setintedge() must be atomic.  Can't disable interrupts from interrupt handlers because they are automatically re-enabled.  Try re-configuring pin instead.

Move LPC17xx IOCON register definitions from lpc17_gpio.h to lpc17_iocon.h; fix a few more .gitignore files

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5815 42af7a65-404d-4744-a932-0658087f49c3

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5814 42af7a65-404d-4744-a932-0658087f49c3

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5813 42af7a65-404d-4744-a932-0658087f49c3

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5812 42af7a65-404d-4744-a932-0658087f49c3

More naming changes associated with earlier renaming of LP17xx up_spiinitialize; LPC178x SSP support; Open1788 SSP and touchscreen support

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5811 42af7a65-404d-4744-a932-0658087f49c3

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5810 42af7a65-404d-4744-a932-0658087f49c3