- Dec 17, 2015
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Gregory Nutt authored
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Gregory Nutt authored
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Gregory Nutt authored
ARMv7-R: Add a configuration to support delayed memory initialization. This logic was already in place for SDRAM but is also required for some ECC memories as well.
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Gregory Nutt authored
ARMv7-R: Add logic to work-around errata, remove logic to access VBAR since this is no VBAR and add logic to access PMCR. TMS570: Add logic to set debug bits in PMCR
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- Dec 16, 2015
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Gregory Nutt authored
TMS570: Memory map applies only to LS04x and LS03x. Peripheral numbering seems to start with 1, not 0
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Gregory Nutt authored
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Gregory Nutt authored
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Gregory Nutt authored
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Gregory Nutt authored
ARMv7-R: fix some issues to get a clean compilation; TMS570: Add enough logic to support a minimum build. Not much there on the initial commit
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- Dec 15, 2015
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Gregory Nutt authored
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Gregory Nutt authored
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Gregory Nutt authored
STM32 QEncoder: Add support for STM32F30xxx
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Gregory Nutt authored
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Paul A. Patience authored
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- Dec 14, 2015
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Gregory Nutt authored
STM32 TIM: Remove some warnings, fix timer resolution bug and cosmetic changes
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Gregory Nutt authored
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Paul A. Patience authored
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Gregory Nutt authored
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Gregory Nutt authored
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Gregory Nutt authored
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Gregory Nutt authored
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Gregory Nutt authored
Rename CONFIG_ARMV7M_MPU to CONFIG_ARM_MPU so that we can reuse the configuration settings for the ARMV7R MPU
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Gregory Nutt authored
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Gregory Nutt authored
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Gregory Nutt authored
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Gregory Nutt authored
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Gregory Nutt authored
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Gregory Nutt authored
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Gregory Nutt authored
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Gregory Nutt authored
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Gregory Nutt authored
STM32: Fix typos in pinmaps
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Gregory Nutt authored
STM32: Fix typos in STM32F30xxx pinmap
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Gregory Nutt authored
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Gregory Nutt authored
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Paul A. Patience authored
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Gregory Nutt authored
Add initial support for ARMv7-R architecture. Initial commit is largely a clone of ARMv7-A and needs further review
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Paul A. Patience authored
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- Dec 12, 2015
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Gregory Nutt authored
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Gregory Nutt authored
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Gregory Nutt authored
All architectures need to build ELF support if either CONFIG_ELF or CONFIG_MODULE are selected. Cortex-M7 also must support module cache corherence
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