- Apr 06, 2017
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Masayuki Ishikawa authored
EFM32 I2C: Fix timeout calculation Approved-by: Gregory Nutt <gnutt@nuttx.org>
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Gregory Nutt authored
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Gregory Nutt authored
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Jussi Kivilinna authored
New interface allows checking if RTC time has been set. This allows to application to detect if RTC has valid time (after reset) or should application attempt to get real time by other means (for example, by launching ntpclient or GPS).
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Gregory Nutt authored
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Frank Benkert authored
According the Datasheet the WDD Value is the lower bound of a so called Forbidden Window and to disable this we have to set the WDD Value greater than or equal to the WDV Value. This seems to be a bug in the datasheet. It looks like we have to set it to a greater value than the WDV to realy disable this Thing. When triggering the Watchdog faster than the (very slow) clock source of the Watchdog fires, this Forbidden Window Feature resets the System if WDD equals to WDV. This Changeset disables the Forbidden Window by setting the WDD Value to the Maximum (0xfff) Value possible.
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Gregory Nutt authored
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Jussi Kivilinna authored
Combination of RXDMA + IFLOWCONTROL does not work as one might expect. Since RXDMA uses circular DMA-buffer, DMA will always keep reading new data from USART peripheral even if DMA buffer underruns. Thus this combination only does following: RTS is asserted on USART setup and deasserted on shutdown and does not perform actual RTS flow-control. Data loss can be demonstrated by doing long up_mdelay inside irq critical section and feeding data to RXDMA+IFLOWCONTROL UART.
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Jussi Kivilinna authored
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Jussi Kivilinna authored
STM32F7: default CONFIG_STM32F7_DMACAPABLE to 'n'. STM32F7 does not have CCM RAM but DTCM, so this option does not need to enabled. DTCM RAM is DMA-able through CPU AHBS bus.
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Jussi Kivilinna authored
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Alan Carvalho de Assis authored
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Gregory Nutt authored
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Masayuki Ishikawa authored
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Masayuki Ishikawa authored
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David Sidrane authored
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Gregory Nutt authored
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- Apr 05, 2017
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Gregory Nutt authored
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Gregory Nutt authored
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Gregory Nutt authored
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Gregory Nutt authored
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Gregory Nutt authored
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Gregory Nutt authored
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Juha Niskanen authored
tm32: stm32l15xxx_rcc: configure medium performance voltage range and zero wait-state when allowed by SYSCLK setting Zero wait-state for flash can be configured when: Range 1 and SYSCLK <= 16 Mhz Range 2 and SYSCLK <= 8 Mhz Range 3 and SYSCLK <= 4.2 Mhz Medium performance voltage range (1.5V) can be configured when SYSCLK is up to 16 Mhz and PLLVCO up to 48 Mhz.
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Juha Niskanen authored
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Hidetaka authored
Fixed gconfig target. Approved-by: Gregory Nutt <gnutt@nuttx.org>
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Hidetaka Takano authored
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Hidetaka authored
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- Apr 04, 2017
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Gregory Nutt authored
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Gregory Nutt authored
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Gregory Nutt authored
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Gregory Nutt authored
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Gregory Nutt authored
6loWPAN: Add option to dump buffers. Fix some issues with calculation of the IEEE802.15.4 header size.
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Gregory Nutt authored
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Juha Niskanen authored
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Juha Niskanen authored
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Jussi Kivilinna authored
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Gregory Nutt authored
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no1wudi authored
STM32:add I2C3 SDA pin mapping for STM32F411 Approved-by: Gregory Nutt <gnutt@nuttx.org>
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no1wudi authored
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