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    • Gregory Nutt's avatar
    • Gregory Nutt's avatar
      Update ChangeLog · 805be6fe
      Gregory Nutt authored
      805be6fe
    • Gregory Nutt's avatar
      The STM32F4Discovery board doesn't come with a Low speed external oscillator... · f1c79423
      Gregory Nutt authored
      The STM32F4Discovery board doesn't come with a Low speed external oscillator so the default LSE source for the RTC doesn't work.
      
      In stm32_rtcc.c the up_rtcinitialize() logic doesn't work with the LSI. The check on RTC_MAGIC on the BK0R register lead to rtc_setup() call that rightfully enables the lsi clock; but the next times, when the rtc is already setup, the rtc_resume() call does NOT start the lsi clock!
      
      The right place to put LSE/LSI initialisation is inside stm32_stdclockconfig() in stm32fxxxxx_rcc.c.  Doing this I checked the possible uses of the LSI and the LSE sources: the LSI can be used for RTC and/or the IWDG, while the LSE only for the RTC (and to output the MCO1 pin)..
      
      This change is not verifed for any other platforms.
      
      From Leo Aloe3132
      f1c79423
    • Gregory Nutt's avatar
      Minor Documentation update · eb304951
      Gregory Nutt authored
      eb304951
    • Gregory Nutt's avatar
      Cortex-M7: Add support for enabled the D-Cache in write only mode. · dab3dbc7
      Gregory Nutt authored
      SAMV7 Ethernet:  I- and D-Cache are now enabled in the netnsh/ configuration.  D-Cache is enabled in write-though mode.  This mode is necessary because the DMA descriptors are each 8-bytes in size but the D-Cache cache line is 32-bits in size. So it is impossible make coherency for every 8-byte DMA descriptor without write-through.
      dab3dbc7