- Aug 19, 2017
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Gregory Nutt authored
commit 2a3ab1652a2c95bcfc8be8380fc7cbdcb6472938 Author: Gregory Nutt <gnutt@nuttx.org> Date: Sat Aug 19 08:44:31 2017 -0600 PF_IEEE802154: Finish some missing bind() logic. Add configs/sim configuration for testing. commit 59be4b846a6e3bfe82087a888e3fdac9c3c414e5 Author: Gregory Nutt <gnutt@nuttx.org> Date: Fri Aug 18 19:30:04 2017 -0600 PF_IEEE802154: More renaming to decouple 6LoPAN from radios in general. commit 69fabb1aea76e54381bdc13de28a3f1441fb42f4 Author: Gregory Nutt <gnutt@nuttx.org> Date: Fri Aug 18 19:21:11 2017 -0600 PF_IEEE802154: Missed a few renamings. commit ff0af1bb25567720934cc1c2a721ccd92cc35f89 Author: Gregory Nutt <gnutt@nuttx.org> Date: Fri Aug 18 17:46:58 2017 -0600 PF_IEEE802154: A few bugfixes commit 01c7c84afd00cf907d280d30cfaf0fb2cf90e02e Author: Gregory Nutt <gnutt@nuttx.org> Date: Fri Aug 18 17:01:31 2017 -0600 PF_IEEE802154: A few bugfixes commit dcef4056d1c1488c93151135f3b7106977faa903 Author: Gre...
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- Aug 18, 2017
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Alan Carvalho de Assis authored
drivers/sensors/hc_sr04.c: Replace busy wait with semaphone. Using this solution we don't need 60ms delay.
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Gregory Nutt authored
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Gregory Nutt authored
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Gregory Nutt authored
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Gregory Nutt authored
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Alan Carvalho de Assis authored
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- Aug 17, 2017
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Gregory Nutt authored
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Gregory Nutt authored
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Gregory Nutt authored
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David Sidrane authored
STM32F7:SDMMC, DMA dcache check in stm32_dmacapable and SDMMC stm32_dma{recv|send}setup Approved-by: Gregory Nutt <gnutt@nuttx.org>
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David Sidrane authored
In the where CONFIG_SDIO_PREFLIGHT is not used and dcache write-buffed mode is used (not write-through) buffer alignment is required for DMA transfers because a) arch_invalidate_dcache could lose buffered writes data and b) arch_flush_dcache could corrupt adjacent memory if the buffer and the bufflen, are not on ARMV7M_DCACHE_LINESIZE boundaries.
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David Sidrane authored
There is no documantation for the STM32F7 that limits DMA on 1 bit vrs 4 bit mode.
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David Sidrane authored
In the case dcache write-buffed mode is used (not write-through) buffer alignment is required for DMA transfers because a) arch_invalidate_dcache could lose buffered writes data and b) arch_flush_dcache could corrupt adjacent memory if the maddr and the mend+1, the next next address are not on ARMV7M_DCACHE_LINESIZE boundaries.
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David Sidrane authored
Updated comment to proper refernce manual for STM32F7 not STM32F4. Added stm32_dmacapable input paramaters documentation.
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David Sidrane authored
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Gregory Nutt authored
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Gregory Nutt authored
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- Aug 16, 2017
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Gregory Nutt authored
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Gregory Nutt authored
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David Sidrane authored
stm32f7:rtc Missing semicolon Approved-by: Gregory Nutt <gnutt@nuttx.org>
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David Sidrane authored
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Gregory Nutt authored
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Gregory Nutt authored
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Gregory Nutt authored
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- Aug 15, 2017
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Gregory Nutt authored
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- Aug 14, 2017
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Arjun Hary authored
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Gregory Nutt authored
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Gregory Nutt authored
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Juha Niskanen authored
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Juha Niskanen authored
STM32L4 DAC: port from STM32. Note that this does not address the somewhat confusing relation between STM32L4_NDACS and DAC2 config macros that comes from original STM32 code.
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Juha Niskanen authored
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Juha Niskanen authored
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- Aug 13, 2017
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Gregory Nutt authored
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Gregory Nutt authored
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Bill Morgan authored
readme: more typo fixes Approved-by: Gregory Nutt <gnutt@nuttx.org>
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Bill Morgan authored
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Gregory Nutt authored
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Sungki Kim authored
fix ESP32 gpio enable reg and default UART pin. Approved-by: Gregory Nutt <gnutt@nuttx.org>
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Sungki Kim authored
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