Improve some ARMv7-A/M floating point register save time; Add floating point register save logic for ARMv7-A

ARMv7-A:  Need 8-byte stack alignment when callign C code from interrupt handlers.  This change needs to be ported to other ARM architectures as well

SAMA5 clock configuration should now agree with Atmel sample code; Added header file with macros to enable and disable peripheral clocking

SAMA5/Cortex-A: Improve irqsave/restore inlines + add irqenable.  Add skeleton file for SAMA5 interrupt management.  Also change from last commit that was left in the editor

Fix some SPI bit bang timing.  I still don't think it is working properly; I am going to need to borrow a logic analyzer