Allow dma in 1 bit mode in STM32F4xxx

STM32: Forgot to update chip.h for STM32F303x[BC]'s 4 ADCs

SMP: Back out deferred IRQ locking.  This was accidentally merged into master and it looks like it is going to be more work than I thought to get it working again.  Changes will go to the irqlock branch.

SMP: Fix logic error in last change:  Deferred restoration of IRQ lock only applies if the context switch was on this CPU.

sched note: record ID enumeration now results on constant values; ID values do not change with configuration.  This makes writing post-processing software much easier

SMP sched_unlock: Should merging depend on g_cpu_irqlock or not?  Let's at least be consistent.  And don't use irqcount; use g_cpu_irqlock.

Xtensa ESP32:  Corrects a problem with dispatching to signal handlers:  Cannot vector directly to the signal handling function as in other ABIs under the Xtensa Window ABI.  In that case, we need to go through a tiny hook when performs the correct window call (call4) otherwise registers will be scrambled in the signal handler

Xtensa ESP32: Some fixes from integration of ostest configuration.  Almost works: There are some assertions in xtensa_sigdeliver()

Xtensa ESP32:  Clock frequency is different if running from IRAM or is booting from FLASH.   This is a booltloader issue.