Add logic for TM4C125GXL clocking based on prototype from from Daniel Carvalho with modifications. I think the LM4F120 may have broken before as well(?).  In any event, the LM4F120 also works well with this chanage

SAMA5 UDPHS: Fix error where bit was not cleared to acknowledge receipt of data and to setup for the next incoming data

SAMA5 clocking:  USB clock setup needs to be done no matter the state of BMS and not matter how we are booting

Kconfig:  Remove warnings.  ARCH_RAMFUNCS depends on ARCH_HAVE_RAMFUNCS, so it is not possible to select ARCH_RAMFUNCS wihtout ARCH_HAVE_RAMFUNCS

SAMA5:  Don't use MMU PMD bufferable bit to try to control write-through vs write-back.  It does not work that way

SAMA5: Update from David Sidrane to last RAM function change:  Apparently inline functions need to placed into the same RAM section, or they do not get inlined.  From David Sidrane

Fix a build error when only USB device tracing is enabled (from David Sidrane).  Also an update to the USB tracing document

SAMA5: On some hardware, reconfiguring the PLL while executing out of NOR FLASH causes crashes.  This was fixed by David Sidrane by implementing RAM functions. The killer code is copied and executed from ISRAM and the crash is avoided.

SAMA5:  When booting from SDRAM, don't copy vectors to ISRAM.  Instread just set the VBAR register to add address of the vectors in SDRAM

If LOWVECTORS is selected, then we need to clear the VBAR register.  A bootloader may have left the VBAR in an bad state

SAMA5: Make sure the MMU and caches are disabled on power up; flush the vector region D-Cache after copying interrupt vectors; make sure that D-Cache, I-Cache, and TLBs are invalidated after modifying the AXI MATRIX remapping