- Oct 06, 2016
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Gregory Nutt authored
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Gregory Nutt authored
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Gregory Nutt authored
configs/stm32l476-mdk/nsh: Remove CONFIG_CXX_INITIALIZE. up_cxxinitialize is not provided in apps/platfor for this board.
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Gregory Nutt authored
configs/olimex-stm32-e407: Add some networking configurations
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Mateusz Szafoni authored
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- Oct 05, 2016
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Gregory Nutt authored
Master l4 usbfix
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David Sidrane authored
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David Sidrane authored
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David Sidrane authored
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- Oct 03, 2016
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Gregory Nutt authored
Add support for qencoders on various nucleo boards
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Sebastien Lorquet authored
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- Oct 02, 2016
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Gregory Nutt authored
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Gregory Nutt authored
Add support for quadrature encoders on STM32L4, including gpio definitions for both directions of timer channels.
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Sebastien Lorquet authored
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Alan Carvalho de Assis authored
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- Oct 01, 2016
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Gregory Nutt authored
sched/pthread and task: When a pthread is started, there is a small bit of logic that will run on the thread of execution of the new pthread. In the case where the new pthread has a lower priority than the parent thread, then this could cause both the parent thread and the new pthread to be blocked at the priority of the lower priority pthread (assuming that CONFIG_PRIORITY_INHERITANCE is not selected). This change temporarily boosts the priority of the new pthread to at least the priority of the new pthread to at least the priority of the parent thread. When that bit of logic has executed on the thread of execution of the new pthread, it will then drop to the correct priority (if necessary) before calling into the new pthread's entry point.
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Gregory Nutt authored
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Gregory Nutt authored
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Neil Hancock authored
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- Sep 30, 2016
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Vytautas Lukenskas authored
There are some small problems in LPC43xx RS485 mode configuration. In particular: 1. UART0,2,3 do not have DTR pins (different from UART1), so, Kconfig needs to be adjusted. 2. lpc43_uart.c in RS485 mode only configures DIR pin, but doesn't enable pin output for UART0,2,3. 3. should be option to reverse DIR control pin output polarity. 4. lpc43xx/chip/lpc43_uart.h doesn't have USART3 definitions. NOTE: I didn't modified and didn't tested USART1, as it has different hardware. From Vytautas Lukenskas.
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- Sep 26, 2016
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Gregory Nutt authored
Add a new ioctl command (set MAXPOS) for tiva QEI
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Young authored
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Young authored
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- Sep 25, 2016
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Gregory Nutt authored
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Gregory Nutt authored
Fix calculations using MSEC_PER_TICK. If USEC_PER_TICK is less than 1000, then MSEC_PER_TICK will be zero. It will be inaccurate in any case.
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- Sep 22, 2016
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Gregory Nutt authored
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Petteri Aimonen authored
libnx/nxglib: Fix handling of near-horizontal lines of width 1 in nxgl_splitline(). Missing handling for degenerate condition caused width 1 lines such as (0, 0) - (100, 10) to have gaps in the drawing.
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Gregory Nutt authored
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Gregory Nutt authored
Corrects a bad assertion noted by Pierre-noel Bouteville. Also fixes a reference counting problem in an error condition: When the mountpoint inode is found but is not an appropriate mountpoint, the reference count on the inode was not being decremented.
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Sagitta Li authored
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Gregory Nutt authored
Remove GPIO_ETH_RMII_TX_CLK. TX_CLK is not present in RMII + sched/: Define 'group' even if HAVE_GROUPID is not set
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Mateusz Szafoni authored
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Mateusz Szafoni authored
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- Sep 21, 2016
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Gregory Nutt authored
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Gregory Nutt authored
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Gregory Nutt authored
Add QEI lower-half driver impl. for Tiva series chip
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Young authored
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Young authored
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- Sep 20, 2016
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Gregory Nutt authored
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Gregory Nutt authored
SAM3/4: Fix GPIO pull-up/down code.
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