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{
register uint32_t __regFaultMask __ASM("faultmask");
return(__regFaultMask);
}
/**
* @brief Set the Fault Mask value
*
* @param faultMask faultMask value
*
* Set the fault mask register
*/
static __INLINE void __set_FAULTMASK(uint32_t faultMask)
{
register uint32_t __regFaultMask __ASM("faultmask");
__regFaultMask = (faultMask & 1);
}
/**
* @brief Return the Control Register value
*
* @return Control value
*
* Return the content of the control register
*/
static __INLINE uint32_t __get_CONTROL(void)
{
register uint32_t __regControl __ASM("control");
return(__regControl);
}
/**
* @brief Set the Control Register value
*
* @param control Control value
*
* Set the control register
*/
static __INLINE void __set_CONTROL(uint32_t control)
{
register uint32_t __regControl __ASM("control");
__regControl = control;
}
#endif /* __ARMCC_VERSION */
#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
#define __enable_irq __enable_interrupt /*!< global Interrupt enable */
#define __disable_irq __disable_interrupt /*!< global Interrupt disable */
static __INLINE void __enable_fault_irq() { __ASM ("cpsie f"); }
static __INLINE void __disable_fault_irq() { __ASM ("cpsid f"); }
#define __NOP __no_operation /*!< no operation intrinsic in IAR Compiler */
static __INLINE void __WFI() { __ASM ("wfi"); }
static __INLINE void __WFE() { __ASM ("wfe"); }
static __INLINE void __SEV() { __ASM ("sev"); }
static __INLINE void __CLREX() { __ASM ("clrex"); }
/* intrinsic void __ISB(void) */
/* intrinsic void __DSB(void) */
/* intrinsic void __DMB(void) */
/* intrinsic void __set_PRIMASK(); */
/* intrinsic void __get_PRIMASK(); */
/* intrinsic void __set_FAULTMASK(); */
/* intrinsic void __get_FAULTMASK(); */
/* intrinsic uint32_t __REV(uint32_t value); */
/* intrinsic uint32_t __REVSH(uint32_t value); */
/* intrinsic unsigned long __STREX(unsigned long, unsigned long); */
/* intrinsic unsigned long __LDREX(unsigned long *); */
/**
* @brief Return the Process Stack Pointer
*
* @return ProcessStackPointer
*
* Return the actual process stack pointer
*/
extern uint32_t __get_PSP(void);
/**
* @brief Set the Process Stack Pointer
*
* @param topOfProcStack Process Stack Pointer
*
* Assign the value ProcessStackPointer to the MSP
* (process stack pointer) Cortex processor register
*/
extern void __set_PSP(uint32_t topOfProcStack);
/**
* @brief Return the Main Stack Pointer
*
* @return Main Stack Pointer
*
* Return the current value of the MSP (main stack pointer)
* Cortex processor register
*/
extern uint32_t __get_MSP(void);
/**
* @brief Set the Main Stack Pointer
*
* @param topOfMainStack Main Stack Pointer
*
* Assign the value mainStackPointer to the MSP
* (main stack pointer) Cortex processor register
*/
extern void __set_MSP(uint32_t topOfMainStack);
/**
* @brief Reverse byte order in unsigned short value
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in unsigned short value
*/
extern uint32_t __REV16(uint16_t value);
/**
* @brief Reverse bit order of value
*
* @param value value to reverse
* @return reversed value
*
* Reverse bit order of value
*/
extern uint32_t __RBIT(uint32_t value);
/**
* @brief LDR Exclusive (8 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 8 bit values)
*/
extern uint8_t __LDREXB(uint8_t *addr);
/**
* @brief LDR Exclusive (16 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 16 bit values
*/
extern uint16_t __LDREXH(uint16_t *addr);
/**
* @brief LDR Exclusive (32 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 32 bit values
*/
extern uint32_t __LDREXW(uint32_t *addr);
/**
* @brief STR Exclusive (8 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 8 bit values
*/
extern uint32_t __STREXB(uint8_t value, uint8_t *addr);
/**
* @brief STR Exclusive (16 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 16 bit values
*/
extern uint32_t __STREXH(uint16_t value, uint16_t *addr);
/**
* @brief STR Exclusive (32 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 32 bit values
*/
extern uint32_t __STREXW(uint32_t value, uint32_t *addr);
#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
static __INLINE void __enable_irq() { __ASM volatile ("cpsie i"); }
static __INLINE void __disable_irq() { __ASM volatile ("cpsid i"); }
static __INLINE void __enable_fault_irq() { __ASM volatile ("cpsie f"); }
static __INLINE void __disable_fault_irq() { __ASM volatile ("cpsid f"); }
static __INLINE void __NOP() { __ASM volatile ("nop"); }
static __INLINE void __WFI() { __ASM volatile ("wfi"); }
static __INLINE void __WFE() { __ASM volatile ("wfe"); }
static __INLINE void __SEV() { __ASM volatile ("sev"); }
static __INLINE void __ISB() { __ASM volatile ("isb"); }
static __INLINE void __DSB() { __ASM volatile ("dsb"); }
static __INLINE void __DMB() { __ASM volatile ("dmb"); }
static __INLINE void __CLREX() { __ASM volatile ("clrex"); }
/**
* @brief Return the Process Stack Pointer
*
* @return ProcessStackPointer
*
* Return the actual process stack pointer
*/
extern uint32_t __get_PSP(void);
/**
* @brief Set the Process Stack Pointer
*
* @param topOfProcStack Process Stack Pointer
*
* Assign the value ProcessStackPointer to the MSP
* (process stack pointer) Cortex processor register
*/
extern void __set_PSP(uint32_t topOfProcStack);
/**
* @brief Return the Main Stack Pointer
*
* @return Main Stack Pointer
*
* Return the current value of the MSP (main stack pointer)
* Cortex processor register
*/
extern uint32_t __get_MSP(void);
/**
* @brief Set the Main Stack Pointer
*
* @param topOfMainStack Main Stack Pointer
*
* Assign the value mainStackPointer to the MSP
* (main stack pointer) Cortex processor register
*/
extern void __set_MSP(uint32_t topOfMainStack);
/**
* @brief Return the Base Priority value
*
* @return BasePriority
*
* Return the content of the base priority register
*/
extern uint32_t __get_BASEPRI(void);
/**
* @brief Set the Base Priority value
*
* @param basePri BasePriority
*
* Set the base priority register
*/
extern void __set_BASEPRI(uint32_t basePri);
/**
* @brief Return the Priority Mask value
*
* @return PriMask
*
* Return state of the priority mask bit from the priority mask register
*/
extern uint32_t __get_PRIMASK(void);
/**
* @brief Set the Priority Mask value
*
* @param priMask PriMask
*
* Set the priority mask bit in the priority mask register
*/
extern void __set_PRIMASK(uint32_t priMask);
/**
* @brief Return the Fault Mask value
*
* @return FaultMask
*
* Return the content of the fault mask register
*/
extern uint32_t __get_FAULTMASK(void);
/**
* @brief Set the Fault Mask value
*
* @param faultMask faultMask value
*
* Set the fault mask register
*/
extern void __set_FAULTMASK(uint32_t faultMask);
/**
* @brief Return the Control Register value
*
* @return Control value
*
* Return the content of the control register
*/
extern uint32_t __get_CONTROL(void);
/**
* @brief Set the Control Register value
*
* @param control Control value
*
* Set the control register
*/
extern void __set_CONTROL(uint32_t control);
/**
* @brief Reverse byte order in integer value
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in integer value
*/
extern uint32_t __REV(uint32_t value);
/**
* @brief Reverse byte order in unsigned short value
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in unsigned short value
*/
extern uint32_t __REV16(uint16_t value);
/**
* @brief Reverse byte order in signed short value with sign extension to integer
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in signed short value with sign extension to integer
*/
extern int32_t __REVSH(int16_t value);
/**
* @brief Reverse bit order of value
*
* @param value value to reverse
* @return reversed value
*
* Reverse bit order of value
*/
extern uint32_t __RBIT(uint32_t value);
/**
* @brief LDR Exclusive (8 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 8 bit value
*/
extern uint8_t __LDREXB(uint8_t *addr);
/**
* @brief LDR Exclusive (16 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 16 bit values
*/
extern uint16_t __LDREXH(uint16_t *addr);
/**
* @brief LDR Exclusive (32 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 32 bit values
*/
extern uint32_t __LDREXW(uint32_t *addr);
/**
* @brief STR Exclusive (8 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 8 bit values
*/
extern uint32_t __STREXB(uint8_t value, uint8_t *addr);
/**
* @brief STR Exclusive (16 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 16 bit values
*/
extern uint32_t __STREXH(uint16_t value, uint16_t *addr);
/**
* @brief STR Exclusive (32 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 32 bit values
*/
extern uint32_t __STREXW(uint32_t value, uint32_t *addr);
#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/
/* TASKING carm specific functions */
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all instrinsics,
* Including the CMSIS ones.
*/
#endif
/** @addtogroup CMSIS_CM3_Core_FunctionInterface CMSIS CM3 Core Function Interface
Core Function Interface containing:
- Core NVIC Functions
- Core SysTick Functions
- Core Reset Functions
*/
/*@{*/
/* ########################## NVIC functions #################################### */
/**
* @brief Set the Priority Grouping in NVIC Interrupt Controller
*
* @param PriorityGroup is priority grouping field
*
* Set the priority grouping field using the required unlock sequence.
* The parameter priority_grouping is assigned to the field
* SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used.
* In case of a conflict between priority grouping and available
* priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
*/
static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
reg_value = SCB->AIRCR; /* read old register configuration */
reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
reg_value = (reg_value |
(0x5FA << SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp << 8)); /* Insert write key and priorty group */
SCB->AIRCR = reg_value;
}
/**
* @brief Get the Priority Grouping from NVIC Interrupt Controller
*
* @return priority grouping field
*
* Get the priority grouping from NVIC Interrupt Controller.
* priority grouping is SCB->AIRCR [10:8] PRIGROUP field.
*/
static __INLINE uint32_t NVIC_GetPriorityGrouping(void)
{
return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
}
/**
* @brief Enable Interrupt in NVIC Interrupt Controller
*
* @param IRQn The positive number of the external interrupt to enable
*
* Enable a device specific interupt in the NVIC interrupt controller.
* The interrupt number cannot be a negative value.
*/
static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
{
NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
}
/**
* @brief Disable the interrupt line for external interrupt specified
*
* @param IRQn The positive number of the external interrupt to disable
*
* Disable a device specific interupt in the NVIC interrupt controller.
* The interrupt number cannot be a negative value.
*/
static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
{
NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
}
/**
* @brief Read the interrupt pending bit for a device specific interrupt source
*
* @param IRQn The number of the device specifc interrupt
* @return 1 = interrupt pending, 0 = interrupt not pending
*
* Read the pending register in NVIC and return 1 if its status is pending,
* otherwise it returns 0
*/
static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
}
/**
* @brief Set the pending bit for an external interrupt
*
* @param IRQn The number of the interrupt for set pending
*
* Set the pending bit for the specified interrupt.
* The interrupt number cannot be a negative value.
*/
static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
}
/**
* @brief Clear the pending bit for an external interrupt
*
* @param IRQn The number of the interrupt for clear pending
*
* Clear the pending bit for the specified interrupt.
* The interrupt number cannot be a negative value.
*/
static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
}
/**
* @brief Read the active bit for an external interrupt
*
* @param IRQn The number of the interrupt for read active bit
* @return 1 = interrupt active, 0 = interrupt not active
*
* Read the active register in NVIC and returns 1 if its status is active,
* otherwise it returns 0.
*/
static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
{
return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
}
/**
* @brief Set the priority for an interrupt
*
* @param IRQn The number of the interrupt for set priority
* @param priority The priority to set
*
* Set the priority for the specified interrupt. The interrupt
* number can be positive to specify an external (device specific)
* interrupt, or negative to specify an internal (core) interrupt.
*
* Note: The priority cannot be set for every core interrupt.
*/
static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if(IRQn < 0) {
SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */
else {
NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
}
/**
* @brief Read the priority for an interrupt
*
* @param IRQn The number of the interrupt for get priority
* @return The priority for the interrupt
*
* Read the priority for the specified interrupt. The interrupt
* number can be positive to specify an external (device specific)
* interrupt, or negative to specify an internal (core) interrupt.
*
* The returned priority value is automatically aligned to the implemented
* priority bits of the microcontroller.
*
* Note: The priority cannot be set for every core interrupt.
*/
static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
{
if(IRQn < 0) {
return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M3 system interrupts */
else {
return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
}
/**
* @brief Encode the priority for an interrupt
*
* @param PriorityGroup The used priority group
* @param PreemptPriority The preemptive priority value (starting from 0)
* @param SubPriority The sub priority value (starting from 0)
* @return The encoded priority for the interrupt
*
* Encode the priority for an interrupt with the given priority group,
* preemptive priority value and sub priority value.
* In case of a conflict between priority grouping and available
* priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
*
* The returned priority value can be used for NVIC_SetPriority(...) function
*/
static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
return (
((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
((SubPriority & ((1 << (SubPriorityBits )) - 1)))
);
}
/**
* @brief Decode the priority of an interrupt
*
* @param Priority The priority for the interrupt
* @param PriorityGroup The used priority group
* @param pPreemptPriority The preemptive priority value (starting from 0)
* @param pSubPriority The sub priority value (starting from 0)
*
* Decode an interrupt priority value with the given priority group to
* preemptive priority value and sub priority value.
* In case of a conflict between priority grouping and available
* priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
*
* The priority value can be retrieved with NVIC_GetPriority(...) function
*/
static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
*pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
*pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
}
/* ################################## SysTick function ############################################ */
#if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0)
/**
* @brief Initialize and start the SysTick counter and its interrupt.
*
* @param ticks number of ticks between two interrupts
* @return 1 = failed, 0 = successful
*
* Initialise the system tick timer and its interrupt and start the
* system tick timer / counter in free running mode to generate
* periodical interrupts.
*/
static __INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */
SysTick->VAL = 0; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0); /* Function successful */
}
#endif
/* ################################## Reset function ############################################ */
/**
* @brief Initiate a system reset request.
*
* Initiate a system reset request to reset the MCU
*/
static __INLINE void NVIC_SystemReset(void)
{
SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
__DSB(); /* Ensure completion of memory access */
while(1); /* wait until reset */
}
/*@}*/ /* end of group CMSIS_CM3_Core_FunctionInterface */
/* ##################################### Debug In/Output function ########################################### */
/** @addtogroup CMSIS_CM3_CoreDebugInterface CMSIS CM3 Core Debug Interface
Core Debug Interface containing:
- Core Debug Receive / Transmit Functions
- Core Debug Defines
- Core Debug Variables
*/
/*@{*/
extern volatile int ITM_RxBuffer; /*!< variable to receive characters */
#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */
/**
* @brief Outputs a character via the ITM channel 0
*
* @param ch character to output
* @return character to output
*
* The function outputs a character via the ITM channel 0.
* The function returns when no debugger is connected that has booked the output.
* It is blocking when a debugger is connected, but the previous character send is not transmitted.
*/
static __INLINE uint32_t ITM_SendChar (uint32_t ch)
{
if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */
(ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
(ITM->TER & (1ul << 0) ) ) /* ITM Port #0 enabled */
{
while (ITM->PORT[0].u32 == 0);
ITM->PORT[0].u8 = (uint8_t) ch;
}
return (ch);
}
/**
* @brief Inputs a character via variable ITM_RxBuffer
*
* @return received character, -1 = no character received
*
* The function inputs a character via variable ITM_RxBuffer.
* The function returns when no debugger is connected that has booked the output.
* It is blocking when a debugger is connected, but the previous character send is not transmitted.
*/
static __INLINE int ITM_ReceiveChar (void) {
int ch = -1; /* no character available */
if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
ch = ITM_RxBuffer;
ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
}
return (ch);
}
/**
* @brief Check if a character via variable ITM_RxBuffer is available
*
* @return 1 = character available, 0 = no character available
*
* The function checks variable ITM_RxBuffer whether a character is available or not.
* The function returns '1' if a character is available and '0' if no character is available.
*/
static __INLINE int ITM_CheckChar (void) {
if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
return (0); /* no character available */
} else {
return (1); /* character available */
}
}
/*@}*/ /* end of group CMSIS_CM3_core_DebugInterface */
#ifdef __cplusplus
}
#endif
/*@}*/ /* end of group CMSIS_CM3_core_definitions */
#endif /* __CM3_CORE_H__ */
/*lint -restore */