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(kicad_pcb (version 4) (host pcbnew 4.0.7)
(general
(links 48)
(no_connects 39)
(area 91.949999 69.924999 208.050001 120.075001)
(thickness 1.6)
(drawings 4)
(tracks 1)
(zones 0)
(modules 20)
(nets 13)
)
(page A4)
(layers
(0 F.Cu signal)
(31 B.Cu signal)
(32 B.Adhes user)
(33 F.Adhes user hide)
(34 B.Paste user)
(35 F.Paste user)
(36 B.SilkS user)
(37 F.SilkS user)
(38 B.Mask user)
(39 F.Mask user hide)
(40 Dwgs.User user)
(41 Cmts.User user)
(42 Eco1.User user)
(43 Eco2.User user)
(44 Edge.Cuts user)
(45 Margin user)
(46 B.CrtYd user)
(47 F.CrtYd user)
(48 B.Fab user)
(49 F.Fab user)
)
(setup
(last_trace_width 0.25)
(trace_clearance 0.2)
(zone_clearance 1)
(zone_45_only no)
(trace_min 0.2)
(segment_width 0.2)
(edge_width 0.15)
(via_size 0.6)
(via_drill 0.4)
(via_min_size 0.4)
(via_min_drill 0.3)
(uvia_size 0.3)
(uvia_drill 0.1)
(uvias_allowed no)
(uvia_min_size 0.2)
(uvia_min_drill 0.1)
(pcb_text_width 0.3)
(pcb_text_size 1.5 1.5)
(mod_edge_width 0.15)
(mod_text_size 1 1)
(mod_text_width 0.15)
(pad_size 1.524 1.524)
(pad_drill 0.762)
(pad_to_mask_clearance 0.2)
(aux_axis_origin 0 0)
(visible_elements 7FFFFFFF)
(pcbplotparams
(layerselection 0x00000_00000001)
(usegerberextensions false)
(excludeedgelayer false)
(linewidth 0.100000)
(plotframeref false)
(viasonmask false)
(mode 1)
(useauxorigin false)
(hpglpennumber 1)
(hpglpenspeed 20)
(hpglpendiameter 15)
(hpglpenoverlay 2)
(psnegative false)
(psa4output false)
(plotreference false)
(plotvalue false)
(plotinvisibletext false)
(padsonsilk false)
(subtractmaskfromsilk false)
(outputformat 1)
(mirror false)
(drillshape 0)
(scaleselection 1)
(outputdirectory gerber/))
)
(net 0 "")
(net 1 GND)
(net 2 VCC)
(net 3 /RF_12)
(net 4 /RF_11)
(net 5 /RF_8)
(net 6 /RF_7)
(net 7 /RF_4)
(net 8 /RF_3)
(net 9 /RF_0)
(net 10 /RF_1)
(net 11 /RF_5)
(net 12 Vadj)
(net_class Default "This is the default net class."
(clearance 0.2)
(trace_width 0.25)
(via_dia 0.6)
(via_drill 0.4)
(uvia_dia 0.3)
(uvia_drill 0.1)
(add_net GND)
(add_net VCC)
(add_net Vadj)
)
(net_class RF ""
(clearance 1)
(trace_width 2.3)
(via_dia 0.6)
(via_drill 0.4)
(uvia_dia 0.3)
(uvia_drill 0.1)
(add_net /RF_0)
(add_net /RF_1)
(add_net /RF_11)
(add_net /RF_12)
(add_net /RF_3)
(add_net /RF_4)
(add_net /RF_5)
(add_net /RF_7)
(add_net /RF_8)
)
(module Connectors_RF:SMA_AMP_132255-12 locked (layer F.Cu) (tedit 58B49D01) (tstamp 5AE17492)
(at 100 98.7 90)
(path /5AE0B196)
(fp_text reference J101 (at 0 11 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value SMA_PCB (at 0 9 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 3.5 -1.5) (end 3.5 0) (layer F.SilkS) (width 0.1))
(fp_line (start 5 -2.5) (end 3.5 -1.5) (layer F.SilkS) (width 0.1))
(fp_line (start 3.5 -3) (end 5 -2.5) (layer F.SilkS) (width 0.1))
(fp_line (start 5 -4) (end 3.5 -3) (layer F.SilkS) (width 0.1))
(fp_line (start 3.5 -4.5) (end 5 -4) (layer F.SilkS) (width 0.1))
(fp_line (start 5 -5.5) (end 3.5 -4.5) (layer F.SilkS) (width 0.1))
(fp_line (start 3.5 -6) (end 5 -5.5) (layer F.SilkS) (width 0.1))
(fp_line (start 3.5 -7) (end 3.5 -6) (layer F.SilkS) (width 0.1))
(fp_line (start -4 -7) (end 3.5 -7) (layer F.SilkS) (width 0.1))
(fp_line (start -4 -6) (end -4 -7) (layer F.SilkS) (width 0.1))
(fp_line (start -5.5 -5.5) (end -4 -6) (layer F.SilkS) (width 0.1))
(fp_line (start -4 -4.5) (end -5.5 -5.5) (layer F.SilkS) (width 0.1))
(fp_line (start -5.5 -4) (end -4 -4.5) (layer F.SilkS) (width 0.1))
(fp_line (start -4 -3) (end -5.5 -4) (layer F.SilkS) (width 0.1))
(fp_line (start -5.5 -2.5) (end -4 -3) (layer F.SilkS) (width 0.1))
(fp_line (start -4 -1.5) (end -5.5 -2.5) (layer F.SilkS) (width 0.1))
(fp_line (start -4 0) (end -4 -1.5) (layer F.SilkS) (width 0.1))
(fp_line (start -5.5 6.5) (end -5.5 0) (layer F.SilkS) (width 0.1))
(fp_line (start -3 6.5) (end -5.5 6.5) (layer F.SilkS) (width 0.1))
(fp_line (start -3 1) (end -3 6.5) (layer F.SilkS) (width 0.1))
(fp_line (start -1.5 1) (end -3 1) (layer F.SilkS) (width 0.1))
(fp_line (start -1.5 6.5) (end -1.5 1) (layer F.SilkS) (width 0.1))
(fp_line (start 1.5 6.5) (end -1.5 6.5) (layer F.SilkS) (width 0.1))
(fp_line (start 1.5 1) (end 1.5 6.5) (layer F.SilkS) (width 0.1))
(fp_line (start 3 1) (end 1.5 1) (layer F.SilkS) (width 0.1))
(fp_line (start 3 6.5) (end 3 1) (layer F.SilkS) (width 0.1))
(fp_line (start 5.5 6.5) (end 3 6.5) (layer F.SilkS) (width 0.1))
(fp_line (start 5.5 0) (end 5.5 6.5) (layer F.SilkS) (width 0.1))
(fp_line (start -5.5 0) (end 5.5 0) (layer F.SilkS) (width 0.1))
(pad 2 smd rect (at -4.25 3.15 90) (size 1.6 4.9) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad 2 smd rect (at 4.25 3.15 90) (size 1.6 4.9) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad 1 smd rect (at 0 2.8 90) (size 1.6 5.6) (layers F.Cu F.Paste F.Mask)
(net 9 /RF_0))
(pad 2 smd rect (at -4.25 3.15 90) (size 1.6 4.9) (layers B.Cu B.Paste B.Mask)
(net 1 GND))
(pad 2 smd rect (at 4.25 3.15 90) (size 1.6 4.9) (layers B.Cu B.Paste B.Mask)
(net 1 GND))
)
(module Connectors_RF:SMA_AMP_132255-12 locked (layer F.Cu) (tedit 58B49D01) (tstamp 5AE174B8)
(at 200 98.7 270)
(path /5AE0F5D4)
(fp_text reference J102 (at 0 11 270) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value SMA_PCB (at 0 9 270) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 3.5 -1.5) (end 3.5 0) (layer F.SilkS) (width 0.1))
(fp_line (start 5 -2.5) (end 3.5 -1.5) (layer F.SilkS) (width 0.1))
(fp_line (start 3.5 -3) (end 5 -2.5) (layer F.SilkS) (width 0.1))
(fp_line (start 5 -4) (end 3.5 -3) (layer F.SilkS) (width 0.1))
(fp_line (start 3.5 -4.5) (end 5 -4) (layer F.SilkS) (width 0.1))
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