Newer
Older
(links 246)
(no_connects 224)
(area 109.924999 68.924999 282.148003 166.981502)
)
(page A4)
(layers
(0 F.Cu signal)
(31 B.Cu signal)
(32 B.Adhes user)
(33 F.Adhes user)
(34 B.Paste user)
(35 F.Paste user)
(36 B.SilkS user)
(37 F.SilkS user)
(38 B.Mask user)
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(40 Dwgs.User user)
(41 Cmts.User user)
(42 Eco1.User user)
(43 Eco2.User user)
(44 Edge.Cuts user)
(45 Margin user)
(46 B.CrtYd user)
(47 F.CrtYd user)
(48 B.Fab user)
(49 F.Fab user)
)
(setup
(last_trace_width 0.25)
(trace_clearance 0.2)
(zone_clearance 0.508)
(zone_45_only no)
(trace_min 0.2)
(segment_width 0.2)
(edge_width 0.15)
(via_size 0.6)
(via_drill 0.4)
(via_min_size 0.4)
(via_min_drill 0.3)
(uvia_size 0.3)
(uvia_drill 0.1)
(uvias_allowed no)
(uvia_min_size 0.2)
(uvia_min_drill 0.1)
(pcb_text_width 0.3)
(pcb_text_size 1.5 1.5)
(mod_edge_width 0.15)
(mod_text_size 1 1)
(mod_text_width 0.15)
(pad_size 1.524 1.524)
(pad_drill 0.762)
(pad_to_mask_clearance 0.2)
(aux_axis_origin 0 0)
(visible_elements 7FFFFFFF)
(pcbplotparams
(layerselection 0x00030_80000001)
(usegerberextensions false)
(excludeedgelayer true)
(linewidth 0.100000)
(plotframeref false)
(viasonmask false)
(mode 1)
(useauxorigin false)
(hpglpennumber 1)
(hpglpenspeed 20)
(hpglpendiameter 15)
(hpglpenoverlay 2)
(psnegative false)
(psa4output false)
(plotreference true)
(plotvalue true)
(plotinvisibletext false)
(padsonsilk false)
(subtractmaskfromsilk false)
(outputformat 1)
(mirror false)
(drillshape 1)
(scaleselection 1)
(outputdirectory ""))
)
(net 0 "")
(net 1 "Net-(C209-Pad1)")
(net 2 GND)
(net 3 "Net-(C210-Pad1)")
(net 4 "Net-(C301-Pad1)")
(net 5 +3.3V)
(net 6 "Net-(C305-Pad1)")
(net 7 /MCU/TMS)
(net 8 /MCU/TCK)
(net 9 /MCU/TDO)
(net 10 /MCU/TDI)
(net 11 /MCU/NRST)
(net 12 /MCU/CS)
(net 13 /MCU/SCK)
(net 14 /MCU/MISO)
(net 15 /MCU/MOSI)
(net 16 /MCU/RF_INT)
(net 17 /MCU/US1_TX)
(net 18 /MCU/US1_RX)
(net 19 VCC)
(net 20 VAMP)
(net 21 Vadj)
(net 22 "Net-(R402-Pad2)")
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(net 23 "Net-(J101-Pad2)")
(net 24 "Net-(J101-Pad4)")
(net 25 "Net-(J101-Pad10)")
(net 26 "Net-(J101-Pad12)")
(net 27 /Si446x_TX/GPIO0)
(net 28 /Si446x_TX/GPIO1)
(net 29 /Si446x_TX/GPIO2)
(net 30 /Si446x_TX/GPIO3)
(net 31 /MCU/PB1)
(net 32 "/Power Amplifier/RF_IN")
(net 33 "/Power Amplifier/RF_OUT")
(net 34 "Net-(C104-Pad1)")
(net 35 "Net-(C104-Pad2)")
(net 36 /MCU/PA_EN)
(net 37 "Net-(Q402-Pad3)")
(net 38 /3.3V_FB)
(net 39 /Si446x_TX/RF_1)
(net 40 /Si446x_TX/RF_2)
(net 41 "Net-(C204-Pad1)")
(net 42 /Si446x_TX/RF_IN)
(net 43 /Si446x_TX/RF_3)
(net 44 /Si446x_TX/RF_4)
(net 45 /Si446x_TX/RF_6)
(net 46 /Si446x_TX/RF_7)
(net 47 +3.3V_RF)
(net 48 /Si446x_TX/RF_5)
(net 49 "Net-(C407-Pad1)")
(net 50 "Net-(C410-Pad2)")
(net 51 "Net-(C411-Pad1)")
(net 52 "Net-(L402-Pad1)")
(net 53 "Net-(L402-Pad2)")
(net 54 "Net-(Q401-Pad1)")
(net 55 "Net-(Z401-Pad1)")
(net 56 "Net-(Z403-Pad2)")
(net 57 "Net-(Z412-Pad2)")
(net 58 "Net-(C216-Pad1)")
(net 59 "Net-(J301-Pad7)")
(net 60 "Net-(U201-Pad5)")
(net 61 "Net-(U201-Pad7)")
(net 62 "Net-(U301-Pad17)")
(net 63 "Net-(U301-Pad23)")
(net 64 "Net-(U301-Pad24)")
(net 65 "Net-(U301-Pad31)")
(net 66 "Net-(U301-Pad32)")
(net 67 /MCU/SCL)
(net 68 /MCU/SDA)
(net 69 +12V)
(net 70 "Net-(C109-Pad1)")
(net 71 "Net-(C109-Pad2)")
(net 72 /8.5V_FB)
(net_class Default "This is the default net class."
(clearance 0.2)
(trace_width 0.25)
(via_dia 0.6)
(via_drill 0.4)
(uvia_dia 0.3)
(uvia_drill 0.1)
(add_net /MCU/CS)
(add_net /MCU/MISO)
(add_net /MCU/MOSI)
(add_net /MCU/NRST)
(add_net /MCU/PB1)
(add_net /MCU/RF_INT)
(add_net /MCU/SCK)
(add_net /MCU/TCK)
(add_net /MCU/TDI)
(add_net /MCU/TDO)
(add_net /MCU/TMS)
(add_net /MCU/US1_RX)
(add_net /MCU/US1_TX)
(add_net "/Power Amplifier/RF_IN")
(add_net "/Power Amplifier/RF_OUT")
(add_net /Si446x_TX/GPIO0)
(add_net /Si446x_TX/GPIO1)
(add_net /Si446x_TX/GPIO2)
(add_net /Si446x_TX/GPIO3)
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