Newer
Older
(links 286)
(no_connects 67)
(area 109.924999 68.924999 190.075001 149.075001)
(1 In1.Cu signal hide)
(2 In2.Cu signal)
(32 B.Adhes user hide)
(33 F.Adhes user hide)
(34 B.Paste user)
(35 F.Paste user)
(36 B.SilkS user)
(37 F.SilkS user)
(38 B.Mask user)
(40 Dwgs.User user)
(41 Cmts.User user)
(42 Eco1.User user)
(43 Eco2.User user)
(44 Edge.Cuts user)
(45 Margin user)
(46 B.CrtYd user)
(47 F.CrtYd user)
(48 B.Fab user)
(49 F.Fab user)
)
(setup
(last_trace_width 0.15)
(trace_clearance 0.15)
(zone_clearance 0.25)
(segment_width 0.2)
(edge_width 0.15)
(via_size 0.6)
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(via_min_size 0.4)
(via_min_drill 0.3)
(uvia_size 0.3)
(uvia_drill 0.1)
(uvias_allowed no)
(uvia_min_size 0.2)
(uvia_min_drill 0.1)
(pcb_text_width 0.3)
(pcb_text_size 1.5 1.5)
(mod_edge_width 0.15)
(mod_text_size 1 1)
(mod_text_width 0.15)
(pad_size 1.524 1.524)
(pad_drill 0.762)
(pad_to_mask_clearance 0.2)
(aux_axis_origin 0 0)
(visible_elements 7FFFFFFF)
(pcbplotparams
(layerselection 0x00030_80000001)
(usegerberextensions false)
(excludeedgelayer true)
(linewidth 0.100000)
(plotframeref false)
(viasonmask false)
(mode 1)
(useauxorigin false)
(hpglpennumber 1)
(hpglpenspeed 20)
(hpglpendiameter 15)
(hpglpenoverlay 2)
(psnegative false)
(psa4output false)
(plotreference true)
(plotvalue true)
(plotinvisibletext false)
(padsonsilk false)
(subtractmaskfromsilk false)
(outputformat 1)
(mirror false)
(drillshape 1)
(scaleselection 1)
(outputdirectory ""))
)
(net 0 "")
(net 1 "Net-(C209-Pad1)")
(net 2 GND)
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(net 3 +3.3V)
(net 4 /MCU/TMS)
(net 5 /MCU/TCK)
(net 6 /MCU/TDO)
(net 7 /MCU/TDI)
(net 8 /MCU/NRST)
(net 9 /MCU/CS)
(net 10 /MCU/SCK)
(net 11 /MCU/MISO)
(net 12 /MCU/MOSI)
(net 13 /MCU/RF_INT)
(net 14 /MCU/US1_TX)
(net 15 /MCU/US1_RX)
(net 16 VCC)
(net 17 VAMP)
(net 18 Vadj)
(net 19 "Net-(R402-Pad2)")
(net 20 /Si446x_TX/GPIO0)
(net 21 /Si446x_TX/GPIO1)
(net 22 /Si446x_TX/GPIO2)
(net 23 /Si446x_TX/GPIO3)
(net 24 /MCU/PB1)
(net 25 "/Power Amplifier/RF_IN")
(net 26 "/Power Amplifier/RF_OUT")
(net 27 "Net-(C104-Pad2)")
(net 28 /MCU/PA_EN)
(net 29 "Net-(Q402-Pad3)")
(net 30 /3.3V_FB)
(net 31 /Si446x_TX/RF_1)
(net 32 /Si446x_TX/RF_2)
(net 33 "Net-(C204-Pad1)")
(net 34 /Si446x_TX/RF_IN)
(net 35 /Si446x_TX/RF_3)
(net 36 /Si446x_TX/RF_4)
(net 37 /Si446x_TX/RF_6)
(net 38 /Si446x_TX/RF_7)
(net 39 +3.3V_RF)
(net 40 /Si446x_TX/RF_5)
(net 41 "Net-(C216-Pad1)")
(net 42 "Net-(J301-Pad7)")
(net 43 "Net-(U201-Pad5)")
(net 44 "Net-(U201-Pad7)")
(net 45 "Net-(U301-Pad17)")
(net 46 +12V)
(net 47 "Net-(C109-Pad2)")
(net 48 /8.5V_FB)
(net 49 /MCU/STM32_CLKIN)
(net 50 "Net-(C209-Pad2)")
(net 51 /MCU/SAFE_LOCK)
(net 52 "Net-(LED301-PadA)")
(net 53 "Net-(LED302-PadA)")
(net 54 "Net-(R109-Pad1)")
(net 55 /SI_CLKIN)
(net 56 /SCL)
(net 57 /SDA)
(net 58 "Net-(R303-Pad1)")
(net 59 "Net-(R304-Pad1)")
(net 60 "Net-(U106-Pad1)")
(net 61 "Net-(U106-Pad7)")
(net 62 "Net-(U108-Pad2)")
(net 63 /PLL_EN)
(net 64 "Net-(U201-Pad16)")
(net 65 "Net-(U301-Pad3)")
(net 66 /rsout_P)
(net 67 /rsout_N)
(net 68 /rsin_N)
(net 69 /rsin_P)
(net 70 /clk_1_P)
(net 71 /clk_P)
(net 72 /clk_N)
(net 73 /clk_1_N)
(net 74 /clk_vbb)
(net 75 /3V3_sw)
(net 76 /12V_sw)
(net 77 "/Power Amplifier/vbias_1")
(net 78 "/Power Amplifier/ibias_1")
(net 79 "/Power Amplifier/vbias_2")
(net 80 "/Power Amplifier/rf_4")
(net 81 "/Power Amplifier/rf_5")
(net 82 "/Power Amplifier/rf_3")
(net 83 "/Power Amplifier/rf_1")
(net 84 "/Power Amplifier/rf_2")
(net 85 "/Power Amplifier/rf_6")
(net 86 "Net-(C119-Pad1)")
(net 87 "Net-(C119-Pad2)")
(net 88 /Si446x_TX/RF_OUT)
(net 89 "Net-(U109-Pad2)")
(net 90 "Net-(U109-Pad5)")
(add_net /MCU/CS)
(add_net /MCU/MISO)
(add_net /MCU/MOSI)
(add_net /MCU/NRST)
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