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\genblk17[17].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(17),
PAD => DDR_DQ(17)
);
\genblk17[18].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(18),
PAD => DDR_DQ(18)
);
\genblk17[19].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(19),
PAD => DDR_DQ(19)
);
\genblk17[1].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(1),
PAD => DDR_DQ(1)
);
\genblk17[20].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(20),
PAD => DDR_DQ(20)
);
\genblk17[21].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(21),
PAD => DDR_DQ(21)
);
\genblk17[22].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(22),
PAD => DDR_DQ(22)
);
\genblk17[23].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(23),
PAD => DDR_DQ(23)
);
\genblk17[24].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(24),
PAD => DDR_DQ(24)
);
\genblk17[25].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(25),
PAD => DDR_DQ(25)
);
\genblk17[26].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(26),
PAD => DDR_DQ(26)
);
\genblk17[27].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(27),
PAD => DDR_DQ(27)
);
\genblk17[28].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(28),
PAD => DDR_DQ(28)
);
\genblk17[29].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(29),
PAD => DDR_DQ(29)
);
\genblk17[2].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(2),
PAD => DDR_DQ(2)
);
\genblk17[30].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(30),
PAD => DDR_DQ(30)
);
\genblk17[31].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(31),
PAD => DDR_DQ(31)
);
\genblk17[3].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(3),
PAD => DDR_DQ(3)
);
\genblk17[4].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(4),
PAD => DDR_DQ(4)
);
\genblk17[5].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(5),
PAD => DDR_DQ(5)
);
\genblk17[6].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(6),
PAD => DDR_DQ(6)
);
\genblk17[7].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(7),
PAD => DDR_DQ(7)
);
\genblk17[8].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(8),
PAD => DDR_DQ(8)
);
\genblk17[9].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(9),
PAD => DDR_DQ(9)
);
\genblk18[0].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(0),
PAD => DDR_DQS_n(0)
);
\genblk18[1].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(1),
PAD => DDR_DQS_n(1)
);
\genblk18[2].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(2),
PAD => DDR_DQS_n(2)
);
\genblk18[3].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(3),
PAD => DDR_DQS_n(3)
);
\genblk19[0].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(0),
PAD => DDR_DQS(0)
);
\genblk19[1].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(1),
PAD => DDR_DQS(1)
);
\genblk19[2].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(2),
PAD => DDR_DQS(2)
);
\genblk19[3].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(3),
PAD => DDR_DQS(3)
);
i_0: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[0]\
);
i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[0]\(1)
);
i_10: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[7]\(1)
);
i_11: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[7]\(0)
);
i_12: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[6]\(1)
);
i_13: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[6]\(0)
);
i_14: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[5]\(1)
);
i_15: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[5]\(0)
);
i_16: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[4]\(1)
);
i_17: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[4]\(0)
);
i_18: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[3]\(1)
);
i_19: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[3]\(0)
);
i_2: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[0]\(0)
);
i_20: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[2]\(1)
);
i_21: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[2]\(0)
);
i_22: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[1]\(1)
);
i_23: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[1]\(0)
);
i_3: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[7]\
);
i_4: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[6]\
);
i_5: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[5]\
);
i_6: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[4]\
);
i_7: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[3]\
);
i_8: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[2]\
);
i_9: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[1]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
I2C0_SDA_I : in STD_LOGIC;
I2C0_SDA_O : out STD_LOGIC;
I2C0_SDA_T : out STD_LOGIC;
I2C0_SCL_I : in STD_LOGIC;
I2C0_SCL_O : out STD_LOGIC;
I2C0_SCL_T : out STD_LOGIC;
SPI1_SCLK_I : in STD_LOGIC;
SPI1_SCLK_O : out STD_LOGIC;
SPI1_SCLK_T : out STD_LOGIC;
SPI1_MOSI_I : in STD_LOGIC;
SPI1_MOSI_O : out STD_LOGIC;
SPI1_MOSI_T : out STD_LOGIC;
SPI1_MISO_I : in STD_LOGIC;
SPI1_MISO_O : out STD_LOGIC;
SPI1_MISO_T : out STD_LOGIC;
SPI1_SS_I : in STD_LOGIC;
SPI1_SS_O : out STD_LOGIC;
SPI1_SS1_O : out STD_LOGIC;
SPI1_SS2_O : out STD_LOGIC;
SPI1_SS_T : out STD_LOGIC;
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_ARREADY : out STD_LOGIC;
S_AXI_HP0_AWREADY : out STD_LOGIC;
S_AXI_HP0_BVALID : out STD_LOGIC;
S_AXI_HP0_RLAST : out STD_LOGIC;
S_AXI_HP0_RVALID : out STD_LOGIC;
S_AXI_HP0_WREADY : out STD_LOGIC;
S_AXI_HP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP0_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_ACLK : in STD_LOGIC;
S_AXI_HP0_ARVALID : in STD_LOGIC;
S_AXI_HP0_AWVALID : in STD_LOGIC;
S_AXI_HP0_BREADY : in STD_LOGIC;
S_AXI_HP0_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP0_RREADY : in STD_LOGIC;
S_AXI_HP0_WLAST : in STD_LOGIC;
S_AXI_HP0_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP0_WVALID : in STD_LOGIC;
S_AXI_HP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP0_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
IRQ_F2P : in STD_LOGIC_VECTOR ( 1 downto 0 );
FCLK_CLK0 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "mz_petalinux_processing_system7_0_0,processing_system7_v5_5_processing_system7,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "processing_system7_v5_5_processing_system7,Vivado 2017.4";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal NLW_inst_CAN0_PHY_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_CAN1_PHY_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA1_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA1_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA1_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA2_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA2_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA2_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA3_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA3_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA3_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_MDIO_MDC_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_MDIO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_MDIO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_SOF_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_SOF_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_MDIO_MDC_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_MDIO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_MDIO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_SOF_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_SOF_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_EVENT_EVENTO_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_CLK1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_CLK2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_CLK3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_RESET1_N_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_RESET2_N_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_RESET3_N_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SCL_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SCL_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SDA_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SDA_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_CAN0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_CAN1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_CTI_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_GPIO_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_I2C0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_I2C1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_QSPI_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SMC_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SPI0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SPI1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_UART0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_UART1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_USB0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_USB1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_PJTAG_TDO_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_BUSPOW_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_CLK_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_CMD_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_CMD_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_LED_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_BUSPOW_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_CLK_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_CMD_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_CMD_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_LED_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MISO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MISO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MOSI_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MOSI_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SCLK_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SCLK_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS1_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS2_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TRACE_CLK_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TRACE_CTL_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART0_DTRN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART0_RTSN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART0_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART1_DTRN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART1_RTSN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART1_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_WDT_RST_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_DMA1_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_DMA2_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_DMA3_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_ENET0_GMII_TXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_ENET1_GMII_TXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_EVENT_STANDBYWFE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_EVENT_STANDBYWFI_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_GPIO_O_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_GPIO_T_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_ARID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_AWID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_M_AXI_GP1_WID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO0_BUSVOLT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_SDIO0_DATA_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO0_DATA_T_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO1_BUSVOLT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_SDIO1_DATA_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO1_DATA_T_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_S_AXI_ACP_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_ACP_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP0_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_S_AXI_GP0_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP1_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_S_AXI_GP1_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP1_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP1_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP2_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP2_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP3_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP3_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_TRACE_DATA_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_USB1_PORT_INDCTL_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_DM_WIDTH : integer;
attribute C_DM_WIDTH of inst : label is 4;
attribute C_DQS_WIDTH : integer;
attribute C_DQS_WIDTH of inst : label is 4;
attribute C_DQ_WIDTH : integer;
attribute C_DQ_WIDTH of inst : label is 32;
attribute C_EMIO_GPIO_WIDTH : integer;
attribute C_EMIO_GPIO_WIDTH of inst : label is 64;
attribute C_EN_EMIO_ENET0 : integer;
attribute C_EN_EMIO_ENET0 of inst : label is 0;
attribute C_EN_EMIO_ENET1 : integer;
attribute C_EN_EMIO_ENET1 of inst : label is 0;
attribute C_EN_EMIO_PJTAG : integer;
attribute C_EN_EMIO_PJTAG of inst : label is 0;
attribute C_EN_EMIO_TRACE : integer;
attribute C_EN_EMIO_TRACE of inst : label is 0;
attribute C_FCLK_CLK0_BUF : string;
attribute C_FCLK_CLK0_BUF of inst : label is "TRUE";
attribute C_FCLK_CLK1_BUF : string;
attribute C_FCLK_CLK1_BUF of inst : label is "FALSE";
attribute C_FCLK_CLK2_BUF : string;
attribute C_FCLK_CLK2_BUF of inst : label is "FALSE";
attribute C_FCLK_CLK3_BUF : string;
attribute C_FCLK_CLK3_BUF of inst : label is "FALSE";
attribute C_GP0_EN_MODIFIABLE_TXN : integer;
attribute C_GP0_EN_MODIFIABLE_TXN of inst : label is 1;
attribute C_GP1_EN_MODIFIABLE_TXN : integer;
attribute C_GP1_EN_MODIFIABLE_TXN of inst : label is 1;
attribute C_INCLUDE_ACP_TRANS_CHECK : integer;
attribute C_INCLUDE_ACP_TRANS_CHECK of inst : label is 0;
attribute C_INCLUDE_TRACE_BUFFER : integer;
attribute C_INCLUDE_TRACE_BUFFER of inst : label is 0;
attribute C_IRQ_F2P_MODE : string;
attribute C_IRQ_F2P_MODE of inst : label is "DIRECT";
attribute C_MIO_PRIMITIVE : integer;
attribute C_MIO_PRIMITIVE of inst : label is 54;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP of inst : label is 0;
attribute C_M_AXI_GP0_ID_WIDTH : integer;
attribute C_M_AXI_GP0_ID_WIDTH of inst : label is 12;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH of inst : label is 12;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP of inst : label is 0;
attribute C_M_AXI_GP1_ID_WIDTH : integer;
attribute C_M_AXI_GP1_ID_WIDTH of inst : label is 12;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH of inst : label is 12;
attribute C_NUM_F2P_INTR_INPUTS : integer;
attribute C_NUM_F2P_INTR_INPUTS of inst : label is 2;
attribute C_PACKAGE_NAME : string;
attribute C_PACKAGE_NAME of inst : label is "clg400";
attribute C_PS7_SI_REV : string;
attribute C_PS7_SI_REV of inst : label is "PRODUCTION";
attribute C_S_AXI_ACP_ARUSER_VAL : integer;
attribute C_S_AXI_ACP_ARUSER_VAL of inst : label is 31;
attribute C_S_AXI_ACP_AWUSER_VAL : integer;
attribute C_S_AXI_ACP_AWUSER_VAL of inst : label is 31;
attribute C_S_AXI_ACP_ID_WIDTH : integer;
attribute C_S_AXI_ACP_ID_WIDTH of inst : label is 3;
attribute C_S_AXI_GP0_ID_WIDTH : integer;
attribute C_S_AXI_GP0_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_GP1_ID_WIDTH : integer;
attribute C_S_AXI_GP1_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP0_DATA_WIDTH : integer;
attribute C_S_AXI_HP0_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP0_ID_WIDTH : integer;
attribute C_S_AXI_HP0_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP1_DATA_WIDTH : integer;
attribute C_S_AXI_HP1_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP1_ID_WIDTH : integer;
attribute C_S_AXI_HP1_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP2_DATA_WIDTH : integer;
attribute C_S_AXI_HP2_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP2_ID_WIDTH : integer;
attribute C_S_AXI_HP2_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP3_DATA_WIDTH : integer;
attribute C_S_AXI_HP3_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP3_ID_WIDTH : integer;
attribute C_S_AXI_HP3_ID_WIDTH of inst : label is 6;
attribute C_TRACE_BUFFER_CLOCK_DELAY : integer;
attribute C_TRACE_BUFFER_CLOCK_DELAY of inst : label is 12;
attribute C_TRACE_BUFFER_FIFO_SIZE : integer;
attribute C_TRACE_BUFFER_FIFO_SIZE of inst : label is 128;
attribute C_TRACE_INTERNAL_WIDTH : integer;
attribute C_TRACE_INTERNAL_WIDTH of inst : label is 2;
attribute C_TRACE_PIPELINE_WIDTH : integer;
attribute C_TRACE_PIPELINE_WIDTH of inst : label is 8;
attribute C_USE_AXI_NONSECURE : integer;
attribute C_USE_AXI_NONSECURE of inst : label is 0;
attribute C_USE_DEFAULT_ACP_USER_VAL : integer;
attribute C_USE_DEFAULT_ACP_USER_VAL of inst : label is 0;
attribute C_USE_M_AXI_GP0 : integer;
attribute C_USE_M_AXI_GP0 of inst : label is 1;
attribute C_USE_M_AXI_GP1 : integer;
attribute C_USE_M_AXI_GP1 of inst : label is 0;
attribute C_USE_S_AXI_ACP : integer;
attribute C_USE_S_AXI_ACP of inst : label is 0;
attribute C_USE_S_AXI_GP0 : integer;
attribute C_USE_S_AXI_GP0 of inst : label is 0;
attribute C_USE_S_AXI_GP1 : integer;
attribute C_USE_S_AXI_GP1 of inst : label is 0;
attribute C_USE_S_AXI_HP0 : integer;
attribute C_USE_S_AXI_HP0 of inst : label is 1;
attribute C_USE_S_AXI_HP1 : integer;
attribute C_USE_S_AXI_HP1 of inst : label is 0;
attribute C_USE_S_AXI_HP2 : integer;
attribute C_USE_S_AXI_HP2 of inst : label is 0;
attribute C_USE_S_AXI_HP3 : integer;
attribute C_USE_S_AXI_HP3 of inst : label is 0;
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of inst : label is "mz_petalinux_processing_system7_0_0.hwdef";
attribute POWER : string;
attribute POWER of inst : label is "<PROCESSOR name={system} numA9Cores={2} clockFreq={667} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={533.333333} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={8} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={111.111110} usageRate={0.5} /><IO interface={SPI} ioStandard={} bidis={2} ioBank={} clockFreq={20.000000} usageRate={0.5} /><IO interface={I2C} ioStandard={} bidis={1} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={8} ioBank={Vcco_p1} clockFreq={25.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={124.999999} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={7} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} /><AXI interface={S_AXI_HP0} dataWidth={64} clockFreq={99} usageRate={0.5} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={99} usageRate={0.5} />/>";
attribute USE_TRACE_DATA_EDGE_DETECTOR : integer;
attribute USE_TRACE_DATA_EDGE_DETECTOR of inst : label is 0;
attribute X_INTERFACE_INFO : string;
attribute X_INTERFACE_INFO of DDR_CAS_n : signal is "xilinx.com:interface:ddrx:1.0 DDR CAS_N";
attribute X_INTERFACE_INFO of DDR_CKE : signal is "xilinx.com:interface:ddrx:1.0 DDR CKE";
attribute X_INTERFACE_INFO of DDR_CS_n : signal is "xilinx.com:interface:ddrx:1.0 DDR CS_N";
attribute X_INTERFACE_INFO of DDR_Clk : signal is "xilinx.com:interface:ddrx:1.0 DDR CK_P";
attribute X_INTERFACE_INFO of DDR_Clk_n : signal is "xilinx.com:interface:ddrx:1.0 DDR CK_N";
attribute X_INTERFACE_INFO of DDR_DRSTB : signal is "xilinx.com:interface:ddrx:1.0 DDR RESET_N";
attribute X_INTERFACE_INFO of DDR_ODT : signal is "xilinx.com:interface:ddrx:1.0 DDR ODT";
attribute X_INTERFACE_INFO of DDR_RAS_n : signal is "xilinx.com:interface:ddrx:1.0 DDR RAS_N";
attribute X_INTERFACE_INFO of DDR_VRN : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN";
attribute X_INTERFACE_INFO of DDR_VRP : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP";
attribute X_INTERFACE_INFO of DDR_WEB : signal is "xilinx.com:interface:ddrx:1.0 DDR WE_N";
attribute X_INTERFACE_INFO of FCLK_CLK0 : signal is "xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK";
attribute X_INTERFACE_PARAMETER : string;
attribute X_INTERFACE_PARAMETER of FCLK_CLK0 : signal is "XIL_INTERFACENAME FCLK_CLK0, FREQ_HZ 99999999, PHASE 0.000, CLK_DOMAIN mz_petalinux_processing_system7_0_0_FCLK_CLK0";
attribute X_INTERFACE_INFO of FCLK_RESET0_N : signal is "xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST";
attribute X_INTERFACE_PARAMETER of FCLK_RESET0_N : signal is "XIL_INTERFACENAME FCLK_RESET0_N, POLARITY ACTIVE_LOW";
attribute X_INTERFACE_INFO of I2C0_SCL_I : signal is "xilinx.com:interface:iic:1.0 IIC_0 SCL_I";
attribute X_INTERFACE_INFO of I2C0_SCL_O : signal is "xilinx.com:interface:iic:1.0 IIC_0 SCL_O";
attribute X_INTERFACE_INFO of I2C0_SCL_T : signal is "xilinx.com:interface:iic:1.0 IIC_0 SCL_T";
attribute X_INTERFACE_INFO of I2C0_SDA_I : signal is "xilinx.com:interface:iic:1.0 IIC_0 SDA_I";
attribute X_INTERFACE_INFO of I2C0_SDA_O : signal is "xilinx.com:interface:iic:1.0 IIC_0 SDA_O";
attribute X_INTERFACE_INFO of I2C0_SDA_T : signal is "xilinx.com:interface:iic:1.0 IIC_0 SDA_T";
attribute X_INTERFACE_INFO of M_AXI_GP0_ACLK : signal is "xilinx.com:signal:clock:1.0 M_AXI_GP0_ACLK CLK";
attribute X_INTERFACE_PARAMETER of M_AXI_GP0_ACLK : signal is "XIL_INTERFACENAME M_AXI_GP0_ACLK, ASSOCIATED_BUSIF M_AXI_GP0, FREQ_HZ 99999999, PHASE 0.000, CLK_DOMAIN mz_petalinux_processing_system7_0_0_FCLK_CLK0";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARREADY : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARREADY";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARVALID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARVALID";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWREADY : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWREADY";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWVALID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWVALID";
attribute X_INTERFACE_INFO of M_AXI_GP0_BREADY : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BREADY";
attribute X_INTERFACE_INFO of M_AXI_GP0_BVALID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BVALID";
attribute X_INTERFACE_INFO of M_AXI_GP0_RLAST : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RLAST";
attribute X_INTERFACE_INFO of M_AXI_GP0_RREADY : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RREADY";
attribute X_INTERFACE_INFO of M_AXI_GP0_RVALID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RVALID";
attribute X_INTERFACE_INFO of M_AXI_GP0_WLAST : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WLAST";
attribute X_INTERFACE_INFO of M_AXI_GP0_WREADY : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WREADY";
attribute X_INTERFACE_INFO of M_AXI_GP0_WVALID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WVALID";
attribute X_INTERFACE_INFO of PS_CLK : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK";
attribute X_INTERFACE_INFO of PS_PORB : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB";
attribute X_INTERFACE_PARAMETER of PS_PORB : signal is "XIL_INTERFACENAME FIXED_IO, CAN_DEBUG false";
attribute X_INTERFACE_INFO of PS_SRSTB : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB";
attribute X_INTERFACE_INFO of SPI1_MISO_I : signal is "xilinx.com:interface:spi:1.0 SPI_1 IO1_I";
attribute X_INTERFACE_INFO of SPI1_MISO_O : signal is "xilinx.com:interface:spi:1.0 SPI_1 IO1_O";
attribute X_INTERFACE_INFO of SPI1_MISO_T : signal is "xilinx.com:interface:spi:1.0 SPI_1 IO1_T";
attribute X_INTERFACE_INFO of SPI1_MOSI_I : signal is "xilinx.com:interface:spi:1.0 SPI_1 IO0_I";
attribute X_INTERFACE_INFO of SPI1_MOSI_O : signal is "xilinx.com:interface:spi:1.0 SPI_1 IO0_O";
attribute X_INTERFACE_INFO of SPI1_MOSI_T : signal is "xilinx.com:interface:spi:1.0 SPI_1 IO0_T";
attribute X_INTERFACE_INFO of SPI1_SCLK_I : signal is "xilinx.com:interface:spi:1.0 SPI_1 SCK_I";
attribute X_INTERFACE_INFO of SPI1_SCLK_O : signal is "xilinx.com:interface:spi:1.0 SPI_1 SCK_O";
attribute X_INTERFACE_INFO of SPI1_SCLK_T : signal is "xilinx.com:interface:spi:1.0 SPI_1 SCK_T";
attribute X_INTERFACE_INFO of SPI1_SS1_O : signal is "xilinx.com:interface:spi:1.0 SPI_1 SS1_O";
attribute X_INTERFACE_INFO of SPI1_SS2_O : signal is "xilinx.com:interface:spi:1.0 SPI_1 SS2_O";
attribute X_INTERFACE_INFO of SPI1_SS_I : signal is "xilinx.com:interface:spi:1.0 SPI_1 SS_I";
attribute X_INTERFACE_INFO of SPI1_SS_O : signal is "xilinx.com:interface:spi:1.0 SPI_1 SS_O";
attribute X_INTERFACE_INFO of SPI1_SS_T : signal is "xilinx.com:interface:spi:1.0 SPI_1 SS_T";
attribute X_INTERFACE_INFO of S_AXI_HP0_ACLK : signal is "xilinx.com:signal:clock:1.0 S_AXI_HP0_ACLK CLK";
attribute X_INTERFACE_PARAMETER of S_AXI_HP0_ACLK : signal is "XIL_INTERFACENAME S_AXI_HP0_ACLK, ASSOCIATED_BUSIF S_AXI_HP0, FREQ_HZ 99999999, PHASE 0.000, CLK_DOMAIN mz_petalinux_processing_system7_0_0_FCLK_CLK0";
attribute X_INTERFACE_INFO of S_AXI_HP0_ARREADY : signal is "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARREADY";
attribute X_INTERFACE_INFO of S_AXI_HP0_ARVALID : signal is "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARVALID";
attribute X_INTERFACE_INFO of S_AXI_HP0_AWREADY : signal is "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWREADY";
attribute X_INTERFACE_INFO of S_AXI_HP0_AWVALID : signal is "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWVALID";
attribute X_INTERFACE_INFO of S_AXI_HP0_BREADY : signal is "xilinx.com:interface:aximm:1.0 S_AXI_HP0 BREADY";
attribute X_INTERFACE_INFO of S_AXI_HP0_BVALID : signal is "xilinx.com:interface:aximm:1.0 S_AXI_HP0 BVALID";
attribute X_INTERFACE_INFO of S_AXI_HP0_RDISSUECAP1_EN : signal is "xilinx.com:display_processing_system7:hpstatusctrl:1.0 S_AXI_HP0_FIFO_CTRL RDISSUECAPEN";
attribute X_INTERFACE_INFO of S_AXI_HP0_RLAST : signal is "xilinx.com:interface:aximm:1.0 S_AXI_HP0 RLAST";
attribute X_INTERFACE_INFO of S_AXI_HP0_RREADY : signal is "xilinx.com:interface:aximm:1.0 S_AXI_HP0 RREADY";
attribute X_INTERFACE_INFO of S_AXI_HP0_RVALID : signal is "xilinx.com:interface:aximm:1.0 S_AXI_HP0 RVALID";
attribute X_INTERFACE_INFO of S_AXI_HP0_WLAST : signal is "xilinx.com:interface:aximm:1.0 S_AXI_HP0 WLAST";
attribute X_INTERFACE_INFO of S_AXI_HP0_WREADY : signal is "xilinx.com:interface:aximm:1.0 S_AXI_HP0 WREADY";
attribute X_INTERFACE_INFO of S_AXI_HP0_WRISSUECAP1_EN : signal is "xilinx.com:display_processing_system7:hpstatusctrl:1.0 S_AXI_HP0_FIFO_CTRL WRISSUECAPEN";
attribute X_INTERFACE_INFO of S_AXI_HP0_WVALID : signal is "xilinx.com:interface:aximm:1.0 S_AXI_HP0 WVALID";
attribute X_INTERFACE_INFO of USB0_VBUS_PWRFAULT : signal is "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRFAULT";
attribute X_INTERFACE_INFO of USB0_VBUS_PWRSELECT : signal is "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRSELECT";
attribute X_INTERFACE_INFO of DDR_Addr : signal is "xilinx.com:interface:ddrx:1.0 DDR ADDR";
attribute X_INTERFACE_INFO of DDR_BankAddr : signal is "xilinx.com:interface:ddrx:1.0 DDR BA";
attribute X_INTERFACE_INFO of DDR_DM : signal is "xilinx.com:interface:ddrx:1.0 DDR DM";
attribute X_INTERFACE_INFO of DDR_DQ : signal is "xilinx.com:interface:ddrx:1.0 DDR DQ";
attribute X_INTERFACE_INFO of DDR_DQS : signal is "xilinx.com:interface:ddrx:1.0 DDR DQS_P";
attribute X_INTERFACE_PARAMETER of DDR_DQS : signal is "XIL_INTERFACENAME DDR, CAN_DEBUG false, TIMEPERIOD_PS 1250, MEMORY_TYPE COMPONENTS, DATA_WIDTH 8, CS_ENABLED true, DATA_MASK_ENABLED true, SLOT Single, MEM_ADDR_MAP ROW_COLUMN_BANK, BURST_LENGTH 8, AXI_ARBITRATION_SCHEME TDM, CAS_LATENCY 11, CAS_WRITE_LATENCY 11";
attribute X_INTERFACE_INFO of DDR_DQS_n : signal is "xilinx.com:interface:ddrx:1.0 DDR DQS_N";
attribute X_INTERFACE_INFO of IRQ_F2P : signal is "xilinx.com:signal:interrupt:1.0 IRQ_F2P INTERRUPT";
attribute X_INTERFACE_PARAMETER of IRQ_F2P : signal is "XIL_INTERFACENAME IRQ_F2P, SENSITIVITY LEVEL_HIGH:NULL, PortWidth 2";
attribute X_INTERFACE_INFO of MIO : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARADDR : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARADDR";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARBURST : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARBURST";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARCACHE : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARCACHE";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARID";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARLEN : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLEN";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARLOCK : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLOCK";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARPROT : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARPROT";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARQOS : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARQOS";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARSIZE : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARSIZE";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWADDR : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWADDR";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWBURST : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWBURST";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWCACHE : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWCACHE";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWID";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWLEN : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLEN";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWLOCK : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLOCK";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWPROT : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWPROT";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWQOS : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWQOS";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWSIZE : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWSIZE";
attribute X_INTERFACE_INFO of M_AXI_GP0_BID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BID";
attribute X_INTERFACE_INFO of M_AXI_GP0_BRESP : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BRESP";
attribute X_INTERFACE_INFO of M_AXI_GP0_RDATA : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RDATA";
attribute X_INTERFACE_PARAMETER of M_AXI_GP0_RDATA : signal is "XIL_INTERFACENAME M_AXI_GP0, SUPPORTS_NARROW_BURST 0, NUM_WRITE_OUTSTANDING 8, NUM_READ_OUTSTANDING 8, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 99999999, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, MAX_BURST_LENGTH 16, PHASE 0.000, CLK_DOMAIN mz_petalinux_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0";
attribute X_INTERFACE_INFO of M_AXI_GP0_RID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RID";
attribute X_INTERFACE_INFO of M_AXI_GP0_RRESP : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RRESP";
attribute X_INTERFACE_INFO of M_AXI_GP0_WDATA : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WDATA";
attribute X_INTERFACE_INFO of M_AXI_GP0_WID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WID";
attribute X_INTERFACE_INFO of M_AXI_GP0_WSTRB : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WSTRB";
attribute X_INTERFACE_INFO of S_AXI_HP0_ARADDR : signal is "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARADDR";
attribute X_INTERFACE_INFO of S_AXI_HP0_ARBURST : signal is "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARBURST";
attribute X_INTERFACE_INFO of S_AXI_HP0_ARCACHE : signal is "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARCACHE";
attribute X_INTERFACE_INFO of S_AXI_HP0_ARID : signal is "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARID";
attribute X_INTERFACE_INFO of S_AXI_HP0_ARLEN : signal is "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARLEN";
attribute X_INTERFACE_INFO of S_AXI_HP0_ARLOCK : signal is "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARLOCK";
attribute X_INTERFACE_INFO of S_AXI_HP0_ARPROT : signal is "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARPROT";
attribute X_INTERFACE_INFO of S_AXI_HP0_ARQOS : signal is "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARQOS";
attribute X_INTERFACE_INFO of S_AXI_HP0_ARSIZE : signal is "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARSIZE";
attribute X_INTERFACE_INFO of S_AXI_HP0_AWADDR : signal is "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWADDR";