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`timescale 1 ns / 1 ps
module LTC2271_SampleGetter_v1_0 #
(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Master Bus Interface M00_AXIS
parameter integer C_M00_AXIS_TDATA_WIDTH = 32,
parameter integer C_M00_AXIS_START_COUNT = 32
)
(
// Users to add ports here
input wire AD_FR_P,
input wire AD_FR_N,
input wire AD_DCO_P,
input wire AD_DCO_N,
input wire AD_IN_1A_P,
input wire AD_IN_1A_N,
input wire AD_IN_1B_P,
input wire AD_IN_1B_N,
input wire AD_IN_1C_P,
input wire AD_IN_1C_N,
input wire AD_IN_1D_P,
input wire AD_IN_1D_N,
input wire AD_IN_2A_P,
input wire AD_IN_2A_N,
input wire AD_IN_2B_P,
input wire AD_IN_2B_N,
input wire AD_IN_2C_P,
input wire AD_IN_2C_N,
input wire AD_IN_2D_P,
input wire AD_IN_2D_N,
// User ports ends
// Do not modify the ports beyond this line
// Ports of Axi Master Bus Interface M00_AXIS
input wire m00_axis_aclk,
input wire m00_axis_aresetn,
output reg m00_axis_tvalid,
output reg [C_M00_AXIS_TDATA_WIDTH-1 : 0] m00_axis_tdata,
output reg [(C_M00_AXIS_TDATA_WIDTH/8)-1 : 0] m00_axis_tstrb,
output reg m00_axis_tlast,
input wire m00_axis_tready
);
/* LTC2271_SampleGetter_v1_0_M00_AXIS # (
.C_M_AXIS_TDATA_WIDTH(C_M00_AXIS_TDATA_WIDTH),
.C_M_START_COUNT(C_M00_AXIS_START_COUNT)
) LTC2271_SampleGetter_v1_0_M00_AXIS_inst (
.M_AXIS_ACLK(m00_axis_aclk),
.M_AXIS_ARESETN(m00_axis_aresetn),
.M_AXIS_TVALID(m00_axis_tvalid),
.M_AXIS_TDATA(m00_axis_tdata),
.M_AXIS_TSTRB(m00_axis_tstrb),
.M_AXIS_TLAST(m00_axis_tlast),
.M_AXIS_TREADY(m00_axis_tready)
);*/
// Add user logic here
/* IO convert */
wire adc_dco, adc_fr, adc1a, adc1b, adc1c, adc1d, adc2a, adc2b, adc2c, adc2d;
IBUFDS #(.DIFF_TERM("TRUE"),.IBUF_LOW_PWR("FALSE"),.IOSTANDARD("DEFAULT")) ADC_DCO_BUF (.O(adc_dco),.IB(AD_DCO_P),.I(AD_DCO_N));
IBUFDS #(.DIFF_TERM("TRUE"),.IBUF_LOW_PWR("FALSE"),.IOSTANDARD("DEFAULT")) ADC_FR_BUF (.O(adc_fr),.IB(AD_FR_P),.I(AD_FR_N));
IBUFDS #(.DIFF_TERM("TRUE"),.IBUF_LOW_PWR("FALSE"),.IOSTANDARD("DEFAULT")) ADC_1A_BUF (.O(adc1a),.IB(AD_IN_1A_P),.I(AD_IN_1A_N));
IBUFDS #(.DIFF_TERM("TRUE"),.IBUF_LOW_PWR("FALSE"),.IOSTANDARD("DEFAULT")) ADC_1B_BUF (.O(adc1b),.IB(AD_IN_1B_P),.I(AD_IN_1B_N));
IBUFDS #(.DIFF_TERM("TRUE"),.IBUF_LOW_PWR("FALSE"),.IOSTANDARD("DEFAULT")) ADC_1C_BUF (.O(adc1c),.IB(AD_IN_1C_P),.I(AD_IN_1C_N));
IBUFDS #(.DIFF_TERM("TRUE"),.IBUF_LOW_PWR("FALSE"),.IOSTANDARD("DEFAULT")) ADC_1D_BUF (.O(adc1d),.IB(AD_IN_1D_P),.I(AD_IN_1D_N));
IBUFDS #(.DIFF_TERM("TRUE"),.IBUF_LOW_PWR("FALSE"),.IOSTANDARD("DEFAULT")) ADC_2A_BUF (.O(adc2a),.IB(AD_IN_2A_P),.I(AD_IN_2A_N));
IBUFDS #(.DIFF_TERM("TRUE"),.IBUF_LOW_PWR("FALSE"),.IOSTANDARD("DEFAULT")) ADC_2B_BUF (.O(adc2b),.IB(AD_IN_2B_P),.I(AD_IN_2B_N));
IBUFDS #(.DIFF_TERM("TRUE"),.IBUF_LOW_PWR("FALSE"),.IOSTANDARD("DEFAULT")) ADC_2C_BUF (.O(adc2c),.IB(AD_IN_2C_P),.I(AD_IN_2C_N));
IBUFDS #(.DIFF_TERM("TRUE"),.IBUF_LOW_PWR("FALSE"),.IOSTANDARD("DEFAULT")) ADC_2D_BUF (.O(adc2d),.IB(AD_IN_2D_P),.I(AD_IN_2D_N));
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/* Extract data using IDDR -> don't forget delay */
wire low_1a, high_1a, low_2a, high_2a, low_3a, high_3a, low_4a, high_4a;
wire low_1b, high_1b, low_2b, high_2b, low_3b, high_3b, low_4b, high_4b;
/* Same Edge Pipelined mode add 1 latency cycle ! */
IDDR #(.DDR_CLK_EDGE("SAME_EDGE_PIPELINED")) DDR_1A (
.C(adc_dco),
.CE(1'b1),
.D(adc1a),
.Q1(low_1a),
.Q2(high_1a)
);
IDDR #(.DDR_CLK_EDGE("SAME_EDGE_PIPELINED")) DDR_2A (
.C(adc_dco),
.CE(1'b1),
.D(adc2a),
.Q1(low_2a),
.Q2(high_2a)
);
IDDR #(.DDR_CLK_EDGE("SAME_EDGE_PIPELINED")) DDR_3A (
.C(adc_dco),
.CE(1'b1),
.D(adc3a),
.Q1(low_3a),
.Q2(high_3a)
);
/* Instantiate FIFO */
/* Test logic */
reg [31:0]cnt = 0;
always @(posedge m00_axis_aclk)
begin
cnt <= cnt + 32'd1;
m00_axis_tdata <= cnt;
m00_axis_tvalid <= 1;
m00_axis_tstrb <= 4'b1111;
m00_axis_tlast <= 0;
end
// User logic ends
endmodule