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LTC2271_SampleGetter_v1_0_control_sets_placed.rpt 2.92 KiB
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Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017
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| Date         : Tue Oct 15 02:05:11 2019
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| Host         : nats-MS-7A72 running 64-bit Ubuntu 18.04.3 LTS
| Command      : report_control_sets -verbose -file LTC2271_SampleGetter_v1_0_control_sets_placed.rpt
| Design       : LTC2271_SampleGetter_v1_0
| Device       : xc7z010
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Control Set Information

Table of Contents
-----------------
1. Summary
2. Flip-Flop Distribution
3. Detailed Control Set Information

1. Summary
----------

+----------------------------------------------------------+-------+
|                          Status                          | Count |
+----------------------------------------------------------+-------+
| Number of unique control sets                            |     1 |
| Unused register locations in slices containing registers |     0 |
+----------------------------------------------------------+-------+


2. Flip-Flop Distribution
-------------------------

+--------------+-----------------------+------------------------+-----------------+--------------+
| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices |
+--------------+-----------------------+------------------------+-----------------+--------------+
| No           | No                    | No                     |              64 |           26 |
| No           | No                    | Yes                    |               0 |            0 |
| No           | Yes                   | No                     |               0 |            0 |
| Yes          | No                    | No                     |               0 |            0 |
| Yes          | No                    | Yes                    |               0 |            0 |
| Yes          | Yes                   | No                     |               0 |            0 |
+--------------+-----------------------+------------------------+-----------------+--------------+


3. Detailed Control Set Information
-----------------------------------

+--------------------------+---------------+------------------+------------------+----------------+
|       Clock Signal       | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count |
+--------------------------+---------------+------------------+------------------+----------------+
|  m00_axis_aclk_IBUF_BUFG |               |                  |               26 |             64 |
+--------------------------+---------------+------------------+------------------+----------------+


+--------+-----------------------+
| Fanout | Number of ControlSets |
+--------+-----------------------+
| 16+    |                     1 |
+--------+-----------------------+