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Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017
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| Host : nats-MS-7A72 running 64-bit Ubuntu 18.04.3 LTS
| Command : report_drc -file LTC2271_SampleGetter_v1_0_drc_opted.rpt -pb LTC2271_SampleGetter_v1_0_drc_opted.pb -rpx LTC2271_SampleGetter_v1_0_drc_opted.rpx
| Design : LTC2271_SampleGetter_v1_0
| Device : xc7z010clg400-1
| Speed File : -1
| Design State : Synthesized
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Report DRC
Table of Contents
-----------------
1. REPORT SUMMARY
2. REPORT DETAILS
1. REPORT SUMMARY
-----------------
Netlist: netlist
Floorplan: design_1
Design limits: <entire design considered>
Ruledeck: default
Max violations: <unlimited>
Violations found: 23
+------------+------------------+----------------------------+------------+
| Rule | Severity | Description | Violations |
+------------+------------------+----------------------------+------------+
| NSTD-1 | Critical Warning | Unspecified I/O Standard | 1 |
| UCIO-1 | Critical Warning | Unconstrained Logical Port | 1 |
| PORTPROP-2 | Warning | selectio_diff_term | 20 |
| ZPS7-1 | Warning | PS7 block required | 1 |
+------------+------------------+----------------------------+------------+
2. REPORT DETAILS
-----------------
NSTD-1#1 Critical Warning
Unspecified I/O Standard
39 out of 39 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: m00_axis_tdata[31:0], m00_axis_tstrb[3:0], m00_axis_aclk, m00_axis_tlast, m00_axis_tvalid.
Related violations: <none>
UCIO-1#1 Critical Warning
Unconstrained Logical Port
39 out of 39 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: m00_axis_tdata[31:0], m00_axis_tstrb[3:0], m00_axis_aclk, m00_axis_tlast, m00_axis_tvalid.
Related violations: <none>
PORTPROP-2#1 Warning
selectio_diff_term
The port AD_DCO_N has an invalid DIFF_TERM property value. For the target architecture, IOSTANDARD value DIFF_HSTL_II_18 does not support on-chip input differential termination. The DIFF_TERM property value will be ignored.
Related violations: <none>
PORTPROP-2#2 Warning
selectio_diff_term
The port AD_DCO_P has an invalid DIFF_TERM property value. For the target architecture, IOSTANDARD value DIFF_HSTL_II_18 does not support on-chip input differential termination. The DIFF_TERM property value will be ignored.
Related violations: <none>
PORTPROP-2#3 Warning
selectio_diff_term
The port AD_FR_N has an invalid DIFF_TERM property value. For the target architecture, IOSTANDARD value DIFF_HSTL_II_18 does not support on-chip input differential termination. The DIFF_TERM property value will be ignored.
Related violations: <none>
PORTPROP-2#4 Warning
selectio_diff_term
The port AD_FR_P has an invalid DIFF_TERM property value. For the target architecture, IOSTANDARD value DIFF_HSTL_II_18 does not support on-chip input differential termination. The DIFF_TERM property value will be ignored.
Related violations: <none>
PORTPROP-2#5 Warning
selectio_diff_term
The port AD_IN_1A_N has an invalid DIFF_TERM property value. For the target architecture, IOSTANDARD value DIFF_HSTL_II_18 does not support on-chip input differential termination. The DIFF_TERM property value will be ignored.
Related violations: <none>
PORTPROP-2#6 Warning
selectio_diff_term
The port AD_IN_1A_P has an invalid DIFF_TERM property value. For the target architecture, IOSTANDARD value DIFF_HSTL_II_18 does not support on-chip input differential termination. The DIFF_TERM property value will be ignored.
Related violations: <none>
PORTPROP-2#7 Warning
selectio_diff_term
The port AD_IN_1B_N has an invalid DIFF_TERM property value. For the target architecture, IOSTANDARD value DIFF_HSTL_II_18 does not support on-chip input differential termination. The DIFF_TERM property value will be ignored.
Related violations: <none>
PORTPROP-2#8 Warning
selectio_diff_term
The port AD_IN_1B_P has an invalid DIFF_TERM property value. For the target architecture, IOSTANDARD value DIFF_HSTL_II_18 does not support on-chip input differential termination. The DIFF_TERM property value will be ignored.
Related violations: <none>
PORTPROP-2#9 Warning
selectio_diff_term
The port AD_IN_1C_N has an invalid DIFF_TERM property value. For the target architecture, IOSTANDARD value DIFF_HSTL_II_18 does not support on-chip input differential termination. The DIFF_TERM property value will be ignored.
Related violations: <none>
PORTPROP-2#10 Warning
selectio_diff_term
The port AD_IN_1C_P has an invalid DIFF_TERM property value. For the target architecture, IOSTANDARD value DIFF_HSTL_II_18 does not support on-chip input differential termination. The DIFF_TERM property value will be ignored.
Related violations: <none>
PORTPROP-2#11 Warning
selectio_diff_term
The port AD_IN_1D_N has an invalid DIFF_TERM property value. For the target architecture, IOSTANDARD value DIFF_HSTL_II_18 does not support on-chip input differential termination. The DIFF_TERM property value will be ignored.
Related violations: <none>
PORTPROP-2#12 Warning
selectio_diff_term
The port AD_IN_1D_P has an invalid DIFF_TERM property value. For the target architecture, IOSTANDARD value DIFF_HSTL_II_18 does not support on-chip input differential termination. The DIFF_TERM property value will be ignored.
Related violations: <none>
PORTPROP-2#13 Warning
selectio_diff_term
The port AD_IN_2A_N has an invalid DIFF_TERM property value. For the target architecture, IOSTANDARD value DIFF_HSTL_II_18 does not support on-chip input differential termination. The DIFF_TERM property value will be ignored.
Related violations: <none>
PORTPROP-2#14 Warning
selectio_diff_term
The port AD_IN_2A_P has an invalid DIFF_TERM property value. For the target architecture, IOSTANDARD value DIFF_HSTL_II_18 does not support on-chip input differential termination. The DIFF_TERM property value will be ignored.
Related violations: <none>
PORTPROP-2#15 Warning
selectio_diff_term
The port AD_IN_2B_N has an invalid DIFF_TERM property value. For the target architecture, IOSTANDARD value DIFF_HSTL_II_18 does not support on-chip input differential termination. The DIFF_TERM property value will be ignored.
Related violations: <none>
PORTPROP-2#16 Warning
selectio_diff_term
The port AD_IN_2B_P has an invalid DIFF_TERM property value. For the target architecture, IOSTANDARD value DIFF_HSTL_II_18 does not support on-chip input differential termination. The DIFF_TERM property value will be ignored.
Related violations: <none>
PORTPROP-2#17 Warning
selectio_diff_term
The port AD_IN_2C_N has an invalid DIFF_TERM property value. For the target architecture, IOSTANDARD value DIFF_HSTL_II_18 does not support on-chip input differential termination. The DIFF_TERM property value will be ignored.
Related violations: <none>
PORTPROP-2#18 Warning
selectio_diff_term
The port AD_IN_2C_P has an invalid DIFF_TERM property value. For the target architecture, IOSTANDARD value DIFF_HSTL_II_18 does not support on-chip input differential termination. The DIFF_TERM property value will be ignored.
Related violations: <none>
PORTPROP-2#19 Warning
selectio_diff_term
The port AD_IN_2D_N has an invalid DIFF_TERM property value. For the target architecture, IOSTANDARD value DIFF_HSTL_II_18 does not support on-chip input differential termination. The DIFF_TERM property value will be ignored.
Related violations: <none>
PORTPROP-2#20 Warning
selectio_diff_term
The port AD_IN_2D_P has an invalid DIFF_TERM property value. For the target architecture, IOSTANDARD value DIFF_HSTL_II_18 does not support on-chip input differential termination. The DIFF_TERM property value will be ignored.
Related violations: <none>
ZPS7-1#1 Warning
PS7 block required
The PS7 cell must be used in this Zynq design in order to enable correct default configuration.
Related violations: <none>