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*** Running vivado
with args -log LTC2271_SampleGetter_v1_0.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source LTC2271_SampleGetter_v1_0.tcl -notrace
****** Vivado v2017.4 (64-bit)
**** SW Build 2086221 on Fri Dec 15 20:54:30 MST 2017
**** IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017
** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
source LTC2271_SampleGetter_v1_0.tcl -notrace
Command: link_design -top LTC2271_SampleGetter_v1_0 -part xc7z010clg400-1
Design is defaulting to srcset: sources_1
Design is defaulting to constrset: constrs_1
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2017.4
INFO: [Device 21-403] Loading part xc7z010clg400-1
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
7 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
link_design completed successfully
link_design: Time (s): cpu = 00:00:08 ; elapsed = 00:00:17 . Memory (MB): peak = 1445.273 ; gain = 263.418 ; free physical = 716 ; free virtual = 10751
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
Running DRC as a precondition to command opt_design
Starting DRC Task
INFO: [DRC 23-27] Running DRC with 4 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
Time (s): cpu = 00:00:00.93 ; elapsed = 00:00:00.75 . Memory (MB): peak = 1495.289 ; gain = 50.016 ; free physical = 705 ; free virtual = 10739
INFO: [Timing 38-35] Done setting XDC timing constraints.
Starting Logic Optimization Task
Phase 1 Retarget
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1941.781 ; gain = 0.000 ; free physical = 334 ; free virtual = 10391
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells
Phase 2 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1941.781 ; gain = 0.000 ; free physical = 334 ; free virtual = 10391
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
Phase 3 Sweep
Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1941.781 ; gain = 0.000 ; free physical = 334 ; free virtual = 10391
INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 12 cells
Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1941.781 ; gain = 0.000 ; free physical = 334 ; free virtual = 10391
INFO: [Opt 31-389] Phase BUFG optimization created 0 cells and removed 0 cells
Phase 5 Shift Register Optimization
Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1941.781 ; gain = 0.000 ; free physical = 334 ; free virtual = 10391
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
Starting Connectivity Check Task
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1941.781 ; gain = 0.000 ; free physical = 334 ; free virtual = 10391
Ending Logic Optimization Task | Checksum: 1416cddf6
Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1941.781 ; gain = 0.000 ; free physical = 334 ; free virtual = 10391
Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1941.781 ; gain = 0.000 ; free physical = 333 ; free virtual = 10391
INFO: [Common 17-83] Releasing license: Implementation
22 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:00:09 ; elapsed = 00:00:16 . Memory (MB): peak = 1941.781 ; gain = 496.508 ; free physical = 333 ; free virtual = 10391
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INFO: [Common 17-1381] The checkpoint '/home/nats/project/VNAV2_Zynq/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/LTC2271_SampleGetter_v1_0_opt.dcp' has been generated.
INFO: [runtcl-4] Executing : report_drc -file LTC2271_SampleGetter_v1_0_drc_opted.rpt -pb LTC2271_SampleGetter_v1_0_drc_opted.pb -rpx LTC2271_SampleGetter_v1_0_drc_opted.rpx
Command: report_drc -file LTC2271_SampleGetter_v1_0_drc_opted.rpt -pb LTC2271_SampleGetter_v1_0_drc_opted.pb -rpx LTC2271_SampleGetter_v1_0_drc_opted.rpx
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/nats/project/VNAV2_Zynq/IP/LTC2271_ADCGetter/LTC2271_SampleGetter_1.0'.
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/nats/project/VNAV2_Zynq/IP/VNA_Config/VNA_Config_1.0'.
WARNING: [IP_Flow 19-2207] Repository '/home/nats/project/VNAV2_Zynq/IP/VNA_Config/VNA_Config_1.0' already exists; ignoring attempt to add it again.
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/nats/project/VNAV2_Zynq/IP/VNA_Config/VNA_Config_1.0'.
WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/nats/project/VNAV2_Zynq/IP/LTC2271_ADCGetter/VNA_PeripheralConfig/VNA_PeripheralConfig_1.0'; Can't find the specified path.
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/home/nats/Xilinx/Vivado/2017.4/data/ip'.
INFO: [DRC 23-27] Running DRC with 4 threads
INFO: [Coretcl 2-168] The results of DRC are in file /home/nats/project/VNAV2_Zynq/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/LTC2271_SampleGetter_v1_0_drc_opted.rpt.
report_drc completed successfully
INFO: [Chipscope 16-241] No debug cores found in the current design.
Before running the implement_debug_core command, either use the Set Up Debug wizard (GUI mode)
or use the create_debug_core and connect_debug_core Tcl commands to insert debug cores into the design.
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
INFO: [DRC 23-27] Running DRC with 4 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
INFO: [DRC 23-27] Running DRC with 4 threads
WARNING: [DRC PORTPROP-2] selectio_diff_term: The port AD_DCO_N has an invalid DIFF_TERM property value. For the target architecture, IOSTANDARD value DIFF_HSTL_II_18 does not support on-chip input differential termination. The DIFF_TERM property value will be ignored.
WARNING: [DRC PORTPROP-2] selectio_diff_term: The port AD_DCO_P has an invalid DIFF_TERM property value. For the target architecture, IOSTANDARD value DIFF_HSTL_II_18 does not support on-chip input differential termination. The DIFF_TERM property value will be ignored.
WARNING: [DRC PORTPROP-2] selectio_diff_term: The port AD_FR_N has an invalid DIFF_TERM property value. For the target architecture, IOSTANDARD value DIFF_HSTL_II_18 does not support on-chip input differential termination. The DIFF_TERM property value will be ignored.
WARNING: [DRC PORTPROP-2] selectio_diff_term: The port AD_FR_P has an invalid DIFF_TERM property value. For the target architecture, IOSTANDARD value DIFF_HSTL_II_18 does not support on-chip input differential termination. The DIFF_TERM property value will be ignored.
WARNING: [DRC PORTPROP-2] selectio_diff_term: The port AD_IN_1A_N has an invalid DIFF_TERM property value. For the target architecture, IOSTANDARD value DIFF_HSTL_II_18 does not support on-chip input differential termination. The DIFF_TERM property value will be ignored.
WARNING: [DRC PORTPROP-2] selectio_diff_term: The port AD_IN_1A_P has an invalid DIFF_TERM property value. For the target architecture, IOSTANDARD value DIFF_HSTL_II_18 does not support on-chip input differential termination. The DIFF_TERM property value will be ignored.
WARNING: [DRC PORTPROP-2] selectio_diff_term: The port AD_IN_1B_N has an invalid DIFF_TERM property value. For the target architecture, IOSTANDARD value DIFF_HSTL_II_18 does not support on-chip input differential termination. The DIFF_TERM property value will be ignored.
WARNING: [DRC PORTPROP-2] selectio_diff_term: The port AD_IN_1B_P has an invalid DIFF_TERM property value. For the target architecture, IOSTANDARD value DIFF_HSTL_II_18 does not support on-chip input differential termination. The DIFF_TERM property value will be ignored.
WARNING: [DRC PORTPROP-2] selectio_diff_term: The port AD_IN_1C_N has an invalid DIFF_TERM property value. For the target architecture, IOSTANDARD value DIFF_HSTL_II_18 does not support on-chip input differential termination. The DIFF_TERM property value will be ignored.
WARNING: [DRC PORTPROP-2] selectio_diff_term: The port AD_IN_1C_P has an invalid DIFF_TERM property value. For the target architecture, IOSTANDARD value DIFF_HSTL_II_18 does not support on-chip input differential termination. The DIFF_TERM property value will be ignored.
WARNING: [DRC PORTPROP-2] selectio_diff_term: The port AD_IN_1D_N has an invalid DIFF_TERM property value. For the target architecture, IOSTANDARD value DIFF_HSTL_II_18 does not support on-chip input differential termination. The DIFF_TERM property value will be ignored.
WARNING: [DRC PORTPROP-2] selectio_diff_term: The port AD_IN_1D_P has an invalid DIFF_TERM property value. For the target architecture, IOSTANDARD value DIFF_HSTL_II_18 does not support on-chip input differential termination. The DIFF_TERM property value will be ignored.
WARNING: [DRC PORTPROP-2] selectio_diff_term: The port AD_IN_2A_N has an invalid DIFF_TERM property value. For the target architecture, IOSTANDARD value DIFF_HSTL_II_18 does not support on-chip input differential termination. The DIFF_TERM property value will be ignored.
WARNING: [DRC PORTPROP-2] selectio_diff_term: The port AD_IN_2A_P has an invalid DIFF_TERM property value. For the target architecture, IOSTANDARD value DIFF_HSTL_II_18 does not support on-chip input differential termination. The DIFF_TERM property value will be ignored.
WARNING: [DRC PORTPROP-2] selectio_diff_term: The port AD_IN_2B_N has an invalid DIFF_TERM property value. For the target architecture, IOSTANDARD value DIFF_HSTL_II_18 does not support on-chip input differential termination. The DIFF_TERM property value will be ignored.
WARNING: [DRC PORTPROP-2] selectio_diff_term: The port AD_IN_2B_P has an invalid DIFF_TERM property value. For the target architecture, IOSTANDARD value DIFF_HSTL_II_18 does not support on-chip input differential termination. The DIFF_TERM property value will be ignored.
WARNING: [DRC PORTPROP-2] selectio_diff_term: The port AD_IN_2C_N has an invalid DIFF_TERM property value. For the target architecture, IOSTANDARD value DIFF_HSTL_II_18 does not support on-chip input differential termination. The DIFF_TERM property value will be ignored.
WARNING: [DRC PORTPROP-2] selectio_diff_term: The port AD_IN_2C_P has an invalid DIFF_TERM property value. For the target architecture, IOSTANDARD value DIFF_HSTL_II_18 does not support on-chip input differential termination. The DIFF_TERM property value will be ignored.
WARNING: [DRC PORTPROP-2] selectio_diff_term: The port AD_IN_2D_N has an invalid DIFF_TERM property value. For the target architecture, IOSTANDARD value DIFF_HSTL_II_18 does not support on-chip input differential termination. The DIFF_TERM property value will be ignored.
WARNING: [DRC PORTPROP-2] selectio_diff_term: The port AD_IN_2D_P has an invalid DIFF_TERM property value. For the target architecture, IOSTANDARD value DIFF_HSTL_II_18 does not support on-chip input differential termination. The DIFF_TERM property value will be ignored.
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 20 Warnings
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Starting Placer Task
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 4 CPUs
Phase 1 Placer Initialization
Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1973.797 ; gain = 0.000 ; free physical = 301 ; free virtual = 10359
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 7a3346c4
Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1973.797 ; gain = 0.000 ; free physical = 301 ; free virtual = 10359
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1973.797 ; gain = 0.000 ; free physical = 301 ; free virtual = 10359
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 155e88f66
Time (s): cpu = 00:00:00.51 ; elapsed = 00:00:00.24 . Memory (MB): peak = 1973.797 ; gain = 0.000 ; free physical = 266 ; free virtual = 10327
Time (s): cpu = 00:00:00.60 ; elapsed = 00:00:00.27 . Memory (MB): peak = 1973.797 ; gain = 0.000 ; free physical = 290 ; free virtual = 10352
Time (s): cpu = 00:00:00.60 ; elapsed = 00:00:00.27 . Memory (MB): peak = 1973.797 ; gain = 0.000 ; free physical = 290 ; free virtual = 10352
Phase 1 Placer Initialization | Checksum: 1c3b1ff4c
Time (s): cpu = 00:00:00.61 ; elapsed = 00:00:00.27 . Memory (MB): peak = 1973.797 ; gain = 0.000 ; free physical = 290 ; free virtual = 10352
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.57 . Memory (MB): peak = 2029.824 ; gain = 56.027 ; free physical = 295 ; free virtual = 10358
Phase 3 Detail Placement
Phase 3.1 Commit Multi Column Macros
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.57 . Memory (MB): peak = 2029.824 ; gain = 56.027 ; free physical = 295 ; free virtual = 10358
Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.58 . Memory (MB): peak = 2029.824 ; gain = 56.027 ; free physical = 295 ; free virtual = 10358
Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.58 . Memory (MB): peak = 2029.824 ; gain = 56.027 ; free physical = 295 ; free virtual = 10358
Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.58 . Memory (MB): peak = 2029.824 ; gain = 56.027 ; free physical = 295 ; free virtual = 10358
Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.62 . Memory (MB): peak = 2029.824 ; gain = 56.027 ; free physical = 293 ; free virtual = 10356
Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.62 . Memory (MB): peak = 2029.824 ; gain = 56.027 ; free physical = 293 ; free virtual = 10356
Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.62 . Memory (MB): peak = 2029.824 ; gain = 56.027 ; free physical = 293 ; free virtual = 10356
Phase 3 Detail Placement | Checksum: 145f087de
Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.62 . Memory (MB): peak = 2029.824 ; gain = 56.027 ; free physical = 293 ; free virtual = 10356
Phase 4 Post Placement Optimization and Clean-Up
Phase 4.1 Post Commit Optimization
Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.62 . Memory (MB): peak = 2029.824 ; gain = 56.027 ; free physical = 293 ; free virtual = 10356
Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.62 . Memory (MB): peak = 2029.824 ; gain = 56.027 ; free physical = 293 ; free virtual = 10356
Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.63 . Memory (MB): peak = 2029.824 ; gain = 56.027 ; free physical = 293 ; free virtual = 10356
Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.63 . Memory (MB): peak = 2029.824 ; gain = 56.027 ; free physical = 293 ; free virtual = 10356
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 145f087de
Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.63 . Memory (MB): peak = 2029.824 ; gain = 56.027 ; free physical = 293 ; free virtual = 10356
Ending Placer Task | Checksum: b9ac0e32
Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.63 . Memory (MB): peak = 2029.824 ; gain = 56.027 ; free physical = 296 ; free virtual = 10359
INFO: [Common 17-83] Releasing license: Implementation
44 Infos, 22 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.11 . Memory (MB): peak = 2029.824 ; gain = 0.000 ; free physical = 294 ; free virtual = 10359
INFO: [Common 17-1381] The checkpoint '/home/nats/project/VNAV2_Zynq/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/LTC2271_SampleGetter_v1_0_placed.dcp' has been generated.
INFO: [runtcl-4] Executing : report_io -file LTC2271_SampleGetter_v1_0_io_placed.rpt
report_io: Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.16 . Memory (MB): peak = 2029.824 ; gain = 0.000 ; free physical = 268 ; free virtual = 10332
INFO: [runtcl-4] Executing : report_utilization -file LTC2271_SampleGetter_v1_0_utilization_placed.rpt -pb LTC2271_SampleGetter_v1_0_utilization_placed.pb
report_utilization: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.11 . Memory (MB): peak = 2029.824 ; gain = 0.000 ; free physical = 267 ; free virtual = 10331
INFO: [runtcl-4] Executing : report_control_sets -verbose -file LTC2271_SampleGetter_v1_0_control_sets_placed.rpt
report_control_sets: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.11 . Memory (MB): peak = 2029.824 ; gain = 0.000 ; free physical = 267 ; free virtual = 10331
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Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
Running DRC as a precondition to command route_design
INFO: [DRC 23-27] Running DRC with 4 threads
WARNING: [DRC PORTPROP-2] selectio_diff_term: The port AD_DCO_N has an invalid DIFF_TERM property value. For the target architecture, IOSTANDARD value DIFF_HSTL_II_18 does not support on-chip input differential termination. The DIFF_TERM property value will be ignored.
WARNING: [DRC PORTPROP-2] selectio_diff_term: The port AD_DCO_P has an invalid DIFF_TERM property value. For the target architecture, IOSTANDARD value DIFF_HSTL_II_18 does not support on-chip input differential termination. The DIFF_TERM property value will be ignored.
WARNING: [DRC PORTPROP-2] selectio_diff_term: The port AD_FR_N has an invalid DIFF_TERM property value. For the target architecture, IOSTANDARD value DIFF_HSTL_II_18 does not support on-chip input differential termination. The DIFF_TERM property value will be ignored.
WARNING: [DRC PORTPROP-2] selectio_diff_term: The port AD_FR_P has an invalid DIFF_TERM property value. For the target architecture, IOSTANDARD value DIFF_HSTL_II_18 does not support on-chip input differential termination. The DIFF_TERM property value will be ignored.
WARNING: [DRC PORTPROP-2] selectio_diff_term: The port AD_IN_1A_N has an invalid DIFF_TERM property value. For the target architecture, IOSTANDARD value DIFF_HSTL_II_18 does not support on-chip input differential termination. The DIFF_TERM property value will be ignored.
WARNING: [DRC PORTPROP-2] selectio_diff_term: The port AD_IN_1A_P has an invalid DIFF_TERM property value. For the target architecture, IOSTANDARD value DIFF_HSTL_II_18 does not support on-chip input differential termination. The DIFF_TERM property value will be ignored.
WARNING: [DRC PORTPROP-2] selectio_diff_term: The port AD_IN_1B_N has an invalid DIFF_TERM property value. For the target architecture, IOSTANDARD value DIFF_HSTL_II_18 does not support on-chip input differential termination. The DIFF_TERM property value will be ignored.
WARNING: [DRC PORTPROP-2] selectio_diff_term: The port AD_IN_1B_P has an invalid DIFF_TERM property value. For the target architecture, IOSTANDARD value DIFF_HSTL_II_18 does not support on-chip input differential termination. The DIFF_TERM property value will be ignored.
WARNING: [DRC PORTPROP-2] selectio_diff_term: The port AD_IN_1C_N has an invalid DIFF_TERM property value. For the target architecture, IOSTANDARD value DIFF_HSTL_II_18 does not support on-chip input differential termination. The DIFF_TERM property value will be ignored.
WARNING: [DRC PORTPROP-2] selectio_diff_term: The port AD_IN_1C_P has an invalid DIFF_TERM property value. For the target architecture, IOSTANDARD value DIFF_HSTL_II_18 does not support on-chip input differential termination. The DIFF_TERM property value will be ignored.
WARNING: [DRC PORTPROP-2] selectio_diff_term: The port AD_IN_1D_N has an invalid DIFF_TERM property value. For the target architecture, IOSTANDARD value DIFF_HSTL_II_18 does not support on-chip input differential termination. The DIFF_TERM property value will be ignored.
WARNING: [DRC PORTPROP-2] selectio_diff_term: The port AD_IN_1D_P has an invalid DIFF_TERM property value. For the target architecture, IOSTANDARD value DIFF_HSTL_II_18 does not support on-chip input differential termination. The DIFF_TERM property value will be ignored.
WARNING: [DRC PORTPROP-2] selectio_diff_term: The port AD_IN_2A_N has an invalid DIFF_TERM property value. For the target architecture, IOSTANDARD value DIFF_HSTL_II_18 does not support on-chip input differential termination. The DIFF_TERM property value will be ignored.
WARNING: [DRC PORTPROP-2] selectio_diff_term: The port AD_IN_2A_P has an invalid DIFF_TERM property value. For the target architecture, IOSTANDARD value DIFF_HSTL_II_18 does not support on-chip input differential termination. The DIFF_TERM property value will be ignored.
WARNING: [DRC PORTPROP-2] selectio_diff_term: The port AD_IN_2B_N has an invalid DIFF_TERM property value. For the target architecture, IOSTANDARD value DIFF_HSTL_II_18 does not support on-chip input differential termination. The DIFF_TERM property value will be ignored.
WARNING: [DRC PORTPROP-2] selectio_diff_term: The port AD_IN_2B_P has an invalid DIFF_TERM property value. For the target architecture, IOSTANDARD value DIFF_HSTL_II_18 does not support on-chip input differential termination. The DIFF_TERM property value will be ignored.
WARNING: [DRC PORTPROP-2] selectio_diff_term: The port AD_IN_2C_N has an invalid DIFF_TERM property value. For the target architecture, IOSTANDARD value DIFF_HSTL_II_18 does not support on-chip input differential termination. The DIFF_TERM property value will be ignored.
WARNING: [DRC PORTPROP-2] selectio_diff_term: The port AD_IN_2C_P has an invalid DIFF_TERM property value. For the target architecture, IOSTANDARD value DIFF_HSTL_II_18 does not support on-chip input differential termination. The DIFF_TERM property value will be ignored.
WARNING: [DRC PORTPROP-2] selectio_diff_term: The port AD_IN_2D_N has an invalid DIFF_TERM property value. For the target architecture, IOSTANDARD value DIFF_HSTL_II_18 does not support on-chip input differential termination. The DIFF_TERM property value will be ignored.
WARNING: [DRC PORTPROP-2] selectio_diff_term: The port AD_IN_2D_P has an invalid DIFF_TERM property value. For the target architecture, IOSTANDARD value DIFF_HSTL_II_18 does not support on-chip input differential termination. The DIFF_TERM property value will be ignored.
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 20 Warnings
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Starting Routing Task
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 4 CPUs
Checksum: PlaceDB: 3f78c76e ConstDB: 0 ShapeSum: 7a3346c4 RouteDB: 0
Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 2051.812 ; gain = 21.988 ; free physical = 198 ; free virtual = 10262
Post Restoration Checksum: NetGraph: 23d02fed NumContArr: ba67171d Constraints: 0 Timing: 0
Phase 2 Router Initialization
INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode.
Phase 2.1 Fix Topology Constraints
Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 2065.812 ; gain = 35.988 ; free physical = 183 ; free virtual = 10248
Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 2065.812 ; gain = 35.988 ; free physical = 183 ; free virtual = 10248
Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 2070.812 ; gain = 40.988 ; free physical = 177 ; free virtual = 10242
Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 2070.812 ; gain = 40.988 ; free physical = 177 ; free virtual = 10242
Phase 4 Rip-up And Reroute
Phase 4.1 Global Iteration 0
Number of Nodes with overlaps = 0
Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 2070.812 ; gain = 40.988 ; free physical = 177 ; free virtual = 10242
Phase 4 Rip-up And Reroute | Checksum: 16ca5cd1d
Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 2070.812 ; gain = 40.988 ; free physical = 177 ; free virtual = 10242
Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 2070.812 ; gain = 40.988 ; free physical = 177 ; free virtual = 10242
Phase 6 Post Hold Fix
Phase 6.1 Hold Fix Iter
Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 2070.812 ; gain = 40.988 ; free physical = 177 ; free virtual = 10242
Phase 6 Post Hold Fix | Checksum: 16ca5cd1d
Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 2070.812 ; gain = 40.988 ; free physical = 177 ; free virtual = 10242
Phase 7 Route finalize
Router Utilization Summary
Global Vertical Routing Utilization = 0.0315315 %
Global Horizontal Routing Utilization = 0.0204504 %
Routable Net Status*
*Does not include unroutable nets such as driverless and loadless.
Run report_route_status for detailed report.
Number of Failed Nets = 0
Number of Unrouted Nets = 0
Number of Partially Routed Nets = 0
Number of Node Overlaps = 0
Utilization threshold used for congestion level computation: 0.85
Congestion Report
North Dir 1x1 Area, Max Cong = 26.1261%, No Congested Regions.
South Dir 1x1 Area, Max Cong = 32.4324%, No Congested Regions.
East Dir 1x1 Area, Max Cong = 10.2941%, No Congested Regions.
West Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions.
Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 2070.812 ; gain = 40.988 ; free physical = 177 ; free virtual = 10242
Phase 8 Verifying routed nets
Verification completed successfully
Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 2072.812 ; gain = 42.988 ; free physical = 176 ; free virtual = 10241
Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 2072.812 ; gain = 42.988 ; free physical = 176 ; free virtual = 10241
Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 2072.812 ; gain = 42.988 ; free physical = 192 ; free virtual = 10257
Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
56 Infos, 42 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 2072.812 ; gain = 42.988 ; free physical = 192 ; free virtual = 10257
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2072.812 ; gain = 0.000 ; free physical = 192 ; free virtual = 10258
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INFO: [Common 17-1381] The checkpoint '/home/nats/project/VNAV2_Zynq/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/LTC2271_SampleGetter_v1_0_routed.dcp' has been generated.
INFO: [runtcl-4] Executing : report_drc -file LTC2271_SampleGetter_v1_0_drc_routed.rpt -pb LTC2271_SampleGetter_v1_0_drc_routed.pb -rpx LTC2271_SampleGetter_v1_0_drc_routed.rpx
Command: report_drc -file LTC2271_SampleGetter_v1_0_drc_routed.rpt -pb LTC2271_SampleGetter_v1_0_drc_routed.pb -rpx LTC2271_SampleGetter_v1_0_drc_routed.rpx
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [DRC 23-27] Running DRC with 4 threads
INFO: [Coretcl 2-168] The results of DRC are in file /home/nats/project/VNAV2_Zynq/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/LTC2271_SampleGetter_v1_0_drc_routed.rpt.
report_drc completed successfully
INFO: [runtcl-4] Executing : report_methodology -file LTC2271_SampleGetter_v1_0_methodology_drc_routed.rpt -pb LTC2271_SampleGetter_v1_0_methodology_drc_routed.pb -rpx LTC2271_SampleGetter_v1_0_methodology_drc_routed.rpx
Command: report_methodology -file LTC2271_SampleGetter_v1_0_methodology_drc_routed.rpt -pb LTC2271_SampleGetter_v1_0_methodology_drc_routed.pb -rpx LTC2271_SampleGetter_v1_0_methodology_drc_routed.rpx
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [DRC 23-133] Running Methodology with 4 threads
INFO: [Coretcl 2-1520] The results of Report Methodology are in file /home/nats/project/VNAV2_Zynq/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/LTC2271_SampleGetter_v1_0_methodology_drc_routed.rpt.
report_methodology completed successfully
INFO: [runtcl-4] Executing : report_power -file LTC2271_SampleGetter_v1_0_power_routed.rpt -pb LTC2271_SampleGetter_v1_0_power_summary_routed.pb -rpx LTC2271_SampleGetter_v1_0_power_routed.rpx
Command: report_power -file LTC2271_SampleGetter_v1_0_power_routed.rpt -pb LTC2271_SampleGetter_v1_0_power_summary_routed.pb -rpx LTC2271_SampleGetter_v1_0_power_routed.rpx
WARNING: [Power 33-232] No user defined clocks were found in the design!
Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate
INFO: [Timing 38-35] Done setting XDC timing constraints.
Running Vector-less Activity Propagation...
Finished Running Vector-less Activity Propagation
68 Infos, 43 Warnings, 0 Critical Warnings and 0 Errors encountered.
report_power completed successfully
INFO: [runtcl-4] Executing : report_route_status -file LTC2271_SampleGetter_v1_0_route_status.rpt -pb LTC2271_SampleGetter_v1_0_route_status.pb
INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file LTC2271_SampleGetter_v1_0_timing_summary_routed.rpt -rpx LTC2271_SampleGetter_v1_0_timing_summary_routed.rpx -warn_on_violation
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 4 CPUs
WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis.
INFO: [runtcl-4] Executing : report_incremental_reuse -file LTC2271_SampleGetter_v1_0_incremental_reuse_routed.rpt
INFO: [Vivado_Tcl 4-545] No incremental reuse to report, no incremental placement and routing data was found.
INFO: [runtcl-4] Executing : report_clock_utilization -file LTC2271_SampleGetter_v1_0_clock_utilization_routed.rpt
INFO: [Common 17-206] Exiting Vivado at Tue Oct 15 02:05:21 2019...