Newer
Older
<GenRun Id="synth_1" LaunchPart="xc7z010clg400-1" LaunchTime="1571097824">
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
<File Type="VDS-TIMING-PB" Name="LTC2271_SampleGetter_v1_0_timing_summary_synth.pb"/>
<File Type="VDS-TIMINGSUMMARY" Name="LTC2271_SampleGetter_v1_0_timing_summary_synth.rpt"/>
<File Type="RDS-DCP" Name="LTC2271_SampleGetter_v1_0.dcp"/>
<File Type="RDS-UTIL-PB" Name="LTC2271_SampleGetter_v1_0_utilization_synth.pb"/>
<File Type="RDS-UTIL" Name="LTC2271_SampleGetter_v1_0_utilization_synth.rpt"/>
<File Type="RDS-PROPCONSTRS" Name="LTC2271_SampleGetter_v1_0_drc_synth.rpt"/>
<File Type="RDS-RDS" Name="LTC2271_SampleGetter_v1_0.vds"/>
<File Type="REPORTS-TCL" Name="LTC2271_SampleGetter_v1_0_reports.tcl"/>
<File Type="PA-TCL" Name="LTC2271_SampleGetter_v1_0.tcl"/>
<FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PPRDIR/LTC2271_SampleGetter_1.0/hdl/LTC2271_SampleGetter_v1_0.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/LTC2271_SampleGetter_1.0/hdl/LTC2271_SampleGetter_v1_0_M00_AXIS.v">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/LTC2271_SampleGetter_1.0/component.xml">
<FileInfo SFType="IPXACT"/>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="LTC2271_SampleGetter_v1_0"/>
<Option Name="TopRTLFile" Val="$PPRDIR/LTC2271_SampleGetter_1.0/hdl/LTC2271_SampleGetter_v1_0.v"/>
</Config>
</FileSet>
<FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
<Filter Type="Constrs"/>
<Config>
<Option Name="ConstrsType" Val="XDC"/>
</Config>
</FileSet>
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2017"/>
<Step Id="synth_design"/>
</Strategy>
</GenRun>