SAMA5: Make sure the MMU and caches are disabled on power up; flush the vector...
SAMA5: Make sure the MMU and caches are disabled on power up; flush the vector region D-Cache after copying interrupt vectors; make sure that D-Cache, I-Cache, and TLBs are invalidated after modifying the AXI MATRIX remapping
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- ChangeLog 9 additions, 0 deletionsChangeLog
- arch/arm/src/armv7-a/arm_head.S 8 additions, 0 deletionsarch/arm/src/armv7-a/arm_head.S
- arch/arm/src/armv7-a/cache.h 4 additions, 4 deletionsarch/arm/src/armv7-a/cache.h
- arch/arm/src/sama5/sam_boot.c 30 additions, 2 deletionsarch/arm/src/sama5/sam_boot.c
- arch/arm/src/sama5/sam_irq.c 34 additions, 0 deletionsarch/arm/src/sama5/sam_irq.c
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