arch/arm/src/lpc54xx: Add configuration logic to the empty SPI driver. Still...

arch/arm/src/lpc54xx:  Add configuration logic to the empty SPI driver.  Still missing all data tranfer logic.

arch/arm/src/lpc54xx/chip/lpc54_spi.h

@@ -260,33 +260,104 @@
 /* Register bit definitions *************************************************************************/
 
 /* SPI Configuration register */
-#define SPI_CFG_
+
+#define SPI_CFG_ENABLE                (1 << 0)  /* Bit 0:  SPI enable */
+#define SPI_CFG_MASTER                (1 << 2)  /* Bit 2:  Master mode select */
+#define SPI_CFG_LSBF                  (1 << 3)  /* Bit 3:  LSB First mode enable */
+#define SPI_CFG_CPHA                  (1 << 4)  /* Bit 4:  Clock Phase select */
+#define SPI_CFG_CPOL                  (1 << 5)  /* Bit 5:  Clock Polarity select */
+#define SPI_CFG_LOOP                  (1 << 7)  /* Bit 7:  Loopback mode enable */
+#define SPI_CFG_SPOL0                 (1 << 8)  /* Bit 8:  SSEL0 Polarity select */
+#define SPI_CFG_SPOL1                 (1 << 9)  /* Bit 9:  SSEL1 Polarity select */
+#define SPI_CFG_SPOL2                 (1 << 10) /* Bit 10: SSEL2 Polarity select */
+#define SPI_CFG_SPOL3                 (1 << 11) /* Bit 11: SSEL3 Polarity select */
+
 /* SPI Delay register */
-#define SPI_DLY_
+
+#define SPI_DLY_PRE_DELAY_SHIFT       (0)       /* Bits 0-3: Time between SSEL assertion and data transfer */
+#define SPI_DLY_PRE_DELAY_MASK        (15 << SPI_DLY_PRE_DELAY_SHIFT)
+#  define SPI_DLY_PRE_DELAY(n)        ((uint32_t)(n) << SPI_DLY_PRE_DELAY_SHIFT)
+#define SPI_DLY_POST_DELAY_SHIFT      (4)       /* Bits 4-7: Time between tdata transfer and SSEL deassertion */
+#define SPI_DLY_POST_DELAY_MASK       (15 << SPI_DLY_POST_DELAY_SHIFT)
+#  define SPI_DLY_POST_DELAY(n)       ((uint32_t)(n) << SPI_DLY_POST_DELAY_SHIFT)
+#define SPI_DLY_FRAME_DELAY_SHIFT     (8)       /* Bits 8-11: Minimum amount of time between frames */
+#define SPI_DLY_FRAME_DELAY_MASK      (15 << SPI_DLY_FRAME_DELAY_SHIFT)
+#  define SPI_DLY_FRAME_DELAY(n)      ((uint32_t)(n) << SPI_DLY_FRAME_DELAY_SHIFT)
+#define SPI_DLY_TRANSFER_DELAY_SHIFT  (12)      /* Bits 12-15: Time SSEL deasserted between transfers */
+#define SPI_DLY_TRANSFER_DELAY_MASK   (15 << SPI_DLY_TRANSFER_DELAY_SHIFT)
+#  define SPI_DLY_TRANSFER_DELAY(n)   ((uint32_t)(n) << SPI_DLY_TRANSFER_DELAY_SHIFT)
+
 /* SPI Status register */
 #define SPI_STAT_
 /* SPI Interrupt Enable read and set */
 #define SPI_INTENSET_
 /* SPI Interrupt Enable Clear */
 #define SPI_INTENCLR_
+
 /* SPI clock Divider */
-#define SPI_DIV_
+
+#define SPI_DIV_SHIFT                 (0)       /* Bits 0-15: Rate divider value */
+#define SPI_DIV_MASK                  (0xffff << SPI_DIV_SHIFT)
+#  define SPI_DIV(n)                  ((uint32_t)((n)-1) << SPI_DIV_SHIFT)
+
 /* SPI Interrupt Status */
 #define SPI_INTSTAT_
+
 /* FIFO configuration and enable register */
-#define SPI_FIFOCFG_
+
+#define SPI_FIFOCFG_ENABLETX          (1 << 0)  /* Bit 0:  Enable the transmit FIFO) */
+#define SPI_FIFOCFG_ENABLERX          (1 << 1)  /* Bit 1:  Enable the receive FIFO) */
+#define SPI_FIFOCFG_SIZE_SHIFT        (4)       /* Bits 4-5:  FIFO size configuration (read-only) */
+#define SPI_FIFOCFG_SIZE_MASK         (3 << SPI_FIFOCFG_SIZE_SHIFT)
+#  define SPI_FIFOCFG_SIZE_8x16       (1 << SPI_FIFOCFG_SIZE_SHIFT) /* FIFO is configured as 8 entries of 16 bits */
+#define SPI_FIFOCFG_DMATX             (1 << 12) /* Bit 12: DMA configuration for transmit */
+#define SPI_FIFOCFG_DMARX             (1 << 13) /* Bit 13: DMA configuration for receive */
+#define SPI_FIFOCFG_WAKETX            (1 << 14) /* Bit 14: Wake-up for transmit FIFO level */
+#define SPI_FIFOCFG_WAKERX            (1 << 15) /* Bit 15: Wake-up for receive FIFO level */
+#define SPI_FIFOCFG_EMPTYTX           (1 << 16) /* Bit 16: Empty command for the transmit FIFO) */
+#define SPI_FIFOCFG_EMPTYRX           (1 << 17) /* Bit 17: Empty command for the receive FIFO) */
+
 /* FIFO status register */
 #define SPI_FIFOSTAT_
+
 /* FIFO trigger level settings for interrupt and DMA request */
-#define SPI_FIFOTRIG_
+
+#define SPI_FIFOTRIG_TXLVLENA         (1 << 0)  /* Bit 0  Transmit FIFO level trigger enable */
+#define SPI_FIFOTRIG_RXLVLENA         (1 << 1)  /* Bit 1  Receive FIFO level trigger enable */
+#define SPI_FIFOTRIG_TXLVL_SHIFT      (8)       /* Bits 8-11: Transmit FIFO level trigger point */
+#define SPI_FIFOTRIG_TXLVL_MASK       (15 << SPI_FIFOTRIG_TXLVL_SHIFT)
+#  define SPI_FIFOTRIG_TXLVL(n)       ((uint32_t)(n) << SPI_FIFOTRIG_TXLVL_SHIFT)
+#  define SPI_FIFOTRIG_TXLVL_EMPTY    (0 << SPI_FIFOTRIG_TXLVL_SHIFT)
+#  define SPI_FIFOTRIG_TXLVL_NOTFULL  (7 << SPI_FIFOTRIG_TXLVL_SHIFT)
+#define SPI_FIFOTRIG_RXLVL_SHIFT      (16)      /* Bits 16-19: Receive FIFO level trigger point */
+#define SPI_FIFOTRIG_RXLVL_MASK       (15 << SPI_FIFOTRIG_RXLVL_SHIFT)
+#  define SPI_FIFOTRIG_RXLVL(n)       ((uint32_t)((n)-1) << SPI_FIFOTRIG_RXLVL_SHIFT)
+#  define SPI_FIFOTRIG_RXLVL_NOTEMPTY (0 << SPI_FIFOTRIG_RXLVL_SHIFT)
+#  define SPI_FIFOTRIG_RXLVL_FULL     (7 << SPI_FIFOTRIG_RXLVL_SHIFT)
+
 /* FIFO interrupt enable set (enable) and read register */
 #define SPI_FIFOINTENSET_
 /* FIFO interrupt enable clear (disable) and read register */
 #define SPI_FIFOINTENCLR_
 /* FIFO interrupt status register */
 #define SPI_FIFOINTSTAT_
+
 /* FIFO write data */
-#define SPI_FIFOWR_
+
+#define SPI_FIFOWR_TXDATA_SHIFT       (0)       /* Bits 0-15: Transmit data to the FIFO */
+#define SPI_FIFOWR_TXDATA_MASK        (0xffff << SPI_FIFOWR_TXDATA_SHIFT)
+#  define SPI_FIFOWR_TXDATA(n)        ((uint32_t)(n) << SPI_FIFOWR_TXDATA_SHIFT)
+#define SPI_FIFOWR_TXSSEL0_N          (1 << 16) /* Bit 16: Transmit Slave Select */
+#define SPI_FIFOWR_TXSSEL1_N          (1 << 17) /* Bit 17: Transmit Slave Select */
+#define SPI_FIFOWR_TXSSEL2_N          (1 << 18) /* Bit 18: Transmit Slave Select */
+#define SPI_FIFOWR_TXSSEL3_N          (1 << 19) /* Bit 19: Transmit Slave Select */
+#define SPI_FIFOWR_EOT                (1 << 20) /* Bit 20: End of Transfer */
+#define SPI_FIFOWR_EOF                (1 << 21) /* Bit 21: End of Frame */
+#define SPI_FIFOWR_RXIGNORE           (1 << 22) /* Bit 22: Receive Ignore */
+#define SPI_FIFOWR_LEN_SHIFT          (24)      /* Bits 24-27: Data Length */
+#define SPI_FIFOWR_LEN_MASK           (15 << SPI_FIFOWR_LEN_SHIFT)
+#  define SPI_FIFOWR_LEN(n)           ((uint32_t)((n)-1) << SPI_FIFOWR_LEN_SHIFT)
+
 /* FIFO read data */
 #define SPI_FIFORD_
 /* FIFO data read with no FIFO pop */

arch/arm/src/lpc54xx/lpc54_spi_master.h

@@ -109,45 +109,111 @@ extern "C"
 FAR struct spi_dev_s *lpc54_spibus_initialize(int port);
 
 /************************************************************************************
- * Name:  lpc54_spiselect, lpc54_spistatus, and lpc54_spicmddata
+ * Name:  lpc54_spiN_select, lpc54_spiN_status, and lpc54_spiN_cmddata
  *
  * Description:
  *   These functions must be provided in your board-specific logic.  The
- *   lpc54_spiselect function will perform chip selection and the lpc54_spistatus
+ *   lpc54_spiN_select function will perform chip selection and the lpc54_spiN_status
  *   will perform status operations using GPIOs in the way your board is configured.
  *
  *   If CONFIG_SPI_CMDDATA is defined in the NuttX configuration, then
- *   lpc54_spicmddata must also be provided.  This functions performs cmd/data
+ *   lpc54_spiN_cmddata must also be provided.  This functions performs cmd/data
  *   selection operations using GPIOs in the way your board is configured.
  *
  ************************************************************************************/
 
-void  lpc54_spiselect(FAR struct spi_dev_s *dev, uint32_t devid, bool selected);
-uint8_t lpc54_spistatus(FAR struct spi_dev_s *dev, uint32_t devid);
+#ifdef CONFIG_LPC54_SPI0_MASTER
+void  lpc54_spi0_select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected);
+uint8_t lpc54_spi0_status(FAR struct spi_dev_s *dev, uint32_t devid);
 
 #ifdef CONFIG_SPI_CMDDATA
-int lpc54_spicmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd);
+int lpc54_spi0_cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd);
+#endif
 #endif
 
-/************************************************************************************
- * Name: spi_flush
- *
- * Description:
- *   Flush and discard any words left in the RX fifo.  This can be called from
- *   spiselect after a device is deselected (if you worry about such things).
- *
- * Input Parameters:
- *   dev - Device-specific state data
- *
- * Returned Value:
- *   None
- *
- ************************************************************************************/
+#ifdef CONFIG_LPC54_SPI1_MASTER
+void  lpc54_spi1_select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected);
+uint8_t lpc54_spi1_status(FAR struct spi_dev_s *dev, uint32_t devid);
+
+#ifdef CONFIG_SPI_CMDDATA
+int lpc54_spi1_cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd);
+#endif
+#endif
+
+#ifdef CONFIG_LPC54_SPI2_MASTER
+void  lpc54_spi2_select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected);
+uint8_t lpc54_spi2_status(FAR struct spi_dev_s *dev, uint32_t devid);
+
+#ifdef CONFIG_SPI_CMDDATA
+int lpc54_spi2_cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd);
+#endif
+#endif
+
+#ifdef CONFIG_LPC54_SPI3_MASTER
+void  lpc54_spi3_select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected);
+uint8_t lpc54_spi3_status(FAR struct spi_dev_s *dev, uint32_t devid);
+
+#ifdef CONFIG_SPI_CMDDATA
+int lpc54_spi3_cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd);
+#endif
+#endif
 
-void spi_flush(FAR struct spi_dev_s *dev);
+#ifdef CONFIG_LPC54_SPI4_MASTER
+void  lpc54_spi4_select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected);
+uint8_t lpc54_spi4_status(FAR struct spi_dev_s *dev, uint32_t devid);
+
+#ifdef CONFIG_SPI_CMDDATA
+int lpc54_spi4_cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd);
+#endif
+#endif
+
+#ifdef CONFIG_LPC54_SPI5_MASTER
+void  lpc54_spi5_select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected);
+uint8_t lpc54_spi5_status(FAR struct spi_dev_s *dev, uint32_t devid);
+
+#ifdef CONFIG_SPI_CMDDATA
+int lpc54_spi5_cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd);
+#endif
+#endif
+
+#ifdef CONFIG_LPC54_SPI6_MASTER
+void  lpc54_spi6_select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected);
+uint8_t lpc54_spi6_status(FAR struct spi_dev_s *dev, uint32_t devid);
+
+#ifdef CONFIG_SPI_CMDDATA
+int lpc54_spi6_cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd);
+#endif
+#endif
+
+#ifdef CONFIG_LPC54_SPI7_MASTER
+void  lpc54_spi7_select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected);
+uint8_t lpc54_spi7_status(FAR struct spi_dev_s *dev, uint32_t devid);
+
+#ifdef CONFIG_SPI_CMDDATA
+int lpc54_spi7_cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd);
+#endif
+#endif
+
+#ifdef CONFIG_LPC54_SPI8_MASTER
+void  lpc54_spi8_select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected);
+uint8_t lpc54_spi8_status(FAR struct spi_dev_s *dev, uint32_t devid);
+
+#ifdef CONFIG_SPI_CMDDATA
+int lpc54_spi8_cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd);
+#endif
+#endif
+
+#ifdef CONFIG_LPC54_SPI9_MASTER
+void  lpc54_spi9_select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected);
+uint8_t lpc54_spi9_status(FAR struct spi_dev_s *dev, uint32_t devid);
+
+#ifdef CONFIG_SPI_CMDDATA
+int lpc54_spi9_cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd);
+#endif
+#endif
 
 /************************************************************************************
- * Name: lpc54_spi/spiregister
+ * Name: lpc54_spiN_register
  *
  * Description:
  *   If the board supports a card detect callback to inform the SPI-based MMC/SD
@@ -167,7 +233,36 @@ void spi_flush(FAR struct spi_dev_s *dev);
  ************************************************************************************/
 
 #ifdef CONFIG_SPI_CALLBACK
-int lpc54_spiregister(FAR struct spi_dev_s *dev, spi_mediachange_t callback, void *arg);
+#ifdef CONFIG_LPC54_SPI0_MASTER
+int lpc54_spi0_register(FAR struct spi_dev_s *dev, spi_mediachange_t callback, void *arg);
+#endif
+#ifdef CONFIG_LPC54_SPI1_MASTER
+int lpc54_spi1_register(FAR struct spi_dev_s *dev, spi_mediachange_t callback, void *arg);
+#endif
+#ifdef CONFIG_LPC54_SPI2_MASTER
+int lpc54_spi2_register(FAR struct spi_dev_s *dev, spi_mediachange_t callback, void *arg);
+#endif
+#ifdef CONFIG_LPC54_SPI3_MASTER
+int lpc54_spi3_register(FAR struct spi_dev_s *dev, spi_mediachange_t callback, void *arg);
+#endif
+#ifdef CONFIG_LPC54_SPI4_MASTER
+int lpc54_spi4_register(FAR struct spi_dev_s *dev, spi_mediachange_t callback, void *arg);
+#endif
+#ifdef CONFIG_LPC54_SPI5_MASTER
+int lpc54_spi5_register(FAR struct spi_dev_s *dev, spi_mediachange_t callback, void *arg);
+#endif
+#ifdef CONFIG_LPC54_SPI6_MASTER
+int lpc54_spi6_register(FAR struct spi_dev_s *dev, spi_mediachange_t callback, void *arg);
+#endif
+#ifdef CONFIG_LPC54_SPI7_MASTER
+int lpc54_spi7_register(FAR struct spi_dev_s *dev, spi_mediachange_t callback, void *arg);
+#endif
+#ifdef CONFIG_LPC54_SPI8_MASTER
+int lpc54_spi8_register(FAR struct spi_dev_s *dev, spi_mediachange_t callback, void *arg);
+#endif
+#ifdef CONFIG_LPC54_SPI9_MASTER
+int lpc54_spi9_register(FAR struct spi_dev_s *dev, spi_mediachange_t callback, void *arg);
+#endif
 #endif
 
 #undef EXTERN

sched/init/os_start.c

@@ -115,7 +115,7 @@ volatile dq_queue_t g_readytorun;
  *    and
  *  - Tasks/threads that have not been assigned to a CPU.
  *
- * Otherwise, the TCB will be reatined in an assigned task list,
+ * Otherwise, the TCB will be retained in an assigned task list,
  * g_assignedtasks.  As its name suggests, on 'g_assignedtasks queue for CPU
  * 'n' would contain only tasks/threads that are assigned to CPU 'n'.  Tasks/
  * threads would be assigned a particular CPU by one of two mechanisms:
@@ -187,7 +187,7 @@ volatile dq_queue_t g_waitingforfill;
 
 volatile dq_queue_t g_inactivetasks;
 
-/* These are lists of dayed memory deallocations that need to be handled
+/* These are lists of delayed memory deallocations that need to be handled
  * within the IDLE loop or worker thread.  These deallocations get queued
  * by sched_kufree and sched_kfree() if the OS needs to deallocate memory
  * while it is within an interrupt handler.