SAMV7: Update floating point and TCM configuration options. Update TODO...

SAMV7:  Update floating point and TCM configuration options.  Update TODO list.  Update comments.  Refresh a configuration

TODO

-NuttX TODO List (Last updated December 29, 2014)
+NuttX TODO List (Last updated March 10, 2015)
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
 This file summarizes known NuttX bugs, limitations, inconsistencies with
@@ -10,9 +10,9 @@ nuttx/
 
  (11)  Task/Scheduler (sched/)
   (1)  Memory Managment (mm/)
-  (3)  Signals (sched/, arch/)
-  (2)  pthreads (sched/)
-  (8)  Kernel/Protected Builds
+  (3)  Signals (sched/signal, arch/)
+  (2)  pthreads (sched/pthread)
+  (1)  Message Queues (sched/mqueue)
   (4)  C++ Support
   (6)  Binary loaders (binfmt/)
  (12)  Network (net/, drivers/net)
@@ -298,7 +298,7 @@ o Memory Managment (mm/)
   Priority:    Medium/Low, a good feature to prevent memory leaks but would
                have negative impact on memory usage and code size.
 
-o Signals (sched/, arch/)
+o Signals (sched/signal, arch/)
   ^^^^^^^^^^^^^^^^^^^^^^^
 
   Title:       STANDARD SIGNALS
@@ -326,7 +326,7 @@ o Signals (sched/, arch/)
   Status:      Open
   Priority:    Low. Even if there are only 31 usable signals, that is still a lot.
 
-o pthreads (sched/)
+o pthreads (sched/pthreads)
   ^^^^^^^^^^^^^^^^^
 
   Title:       CANCELLATION POINTS
@@ -393,6 +393,25 @@ o pthreads (sched/)
                solution. So I discarded a few hours of programming. Not a
                big loss from the experience I gained."
 
+Message Queues (sched/mqueue)
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+  Title:       mq_timedsend() ERROR DETECTION
+  Description: mq_timedsend() will always return an error an invalid time is
+               provided.  However, OpenGroup.org says:
+
+               "Under no circumstance shall the operation fail with a timeout
+                if there is sufficient room in the queue to add the message
+                immediately. The validity of the abstime parameter need not be
+                checked when there is sufficient room in the queue."
+
+  Status:       Open
+  Priority:     Low.  This is a valid POSIX compliance issue, but not thought
+                to be really important in real work programming.  It could
+                be used to conditionally block like O_NONBLOCK by providing a
+                bad time to the function.  That seeks hokey and I can't think
+                of any other real world use case the demands this functionality.
+
 o Kernel/Protected Build
   ^^^^^^^^^^^^^^^^^^^^^^
 

arch/arm/Kconfig

@@ -348,13 +348,26 @@ config ARCH_HAVE_FPU
 	bool
 	default n
 
+config ARCH_HAVE_DPFPU
+	bool
+	default n
+
 config ARCH_FPU
 	bool "FPU support"
 	default y
 	depends on ARCH_HAVE_FPU
 	---help---
 		Build in support for the ARM Cortex-M4 Floating Point Unit (FPU).
-		Check your chip specifications first; not all Cortex-M4 chips support the FPU.
+		Check your chip specifications first; not all Cortex-M4 chips
+		support the FPU.
+
+config ARCH_DPFPU
+	bool "Double precision FPU support"
+	default y
+	depends on ARCH_FPU && ARCH_HAVE_DPFPU
+	---help---
+		Enable toolchain support for double precision (64-bit) floating
+		point if both the toolchain and the hardware support it.
 
 config ARMV7M_MPU
 	bool "MPU support"

arch/arm/src/armv7-m/Kconfig

@@ -23,6 +23,24 @@ config ARMV7M_DCACHE
 	default n
 	depends on ARMV7M_HAVE_DCACHE
 
+config ARMV7M_HAVE_ITCM
+	bool
+	default n
+
+config ARMV7M_HAVE_DTCM
+	bool
+	default n
+
+config ARMV7M_ITCM
+	bool "Use ITCM"
+	default n
+	depends on ARMV7M_HAVE_ITCM
+
+config ARMV7M_DTCM
+	bool "Use DTCM"
+	default n
+	depends on ARMV7M_HAVE_DTCM
+
 choice
 	prompt "Toolchain Selection"
 	default ARMV7M_TOOLCHAIN_GNU_EABIW if HOST_WINDOWS

arch/arm/src/armv7-m/Toolchain.defs

@@ -128,7 +128,11 @@ ifeq ($(CONFIG_ARCH_CORTEXM4),y)
   TOOLCHAIN_MTUNE    := -mtune=cortex-m4
   TOOLCHAIN_MARCH    := -march=armv7e-m
   ifeq ($(CONFIG_ARCH_FPU),y)
+  ifeq ($(CONFIG_ARCH_DPFPU),y)
+    TOOLCHAIN_MFLOAT := -mfpu=fpv4-sp -mfloat-abi=hard
+  else
     TOOLCHAIN_MFLOAT := -mfpu=fpv4-sp-d16 -mfloat-abi=hard
+  endif
   else
     TOOLCHAIN_MFLOAT := -mfloat-abi=soft
   endif
@@ -140,9 +144,13 @@ else ifeq ($(CONFIG_ARCH_CORTEXM7),y)
   TOOLCHAIN_MCPU     := -mcpu=cortex-m4
   TOOLCHAIN_MTUNE    := -mtune=cortex-m4
   TOOLCHAIN_MARCH    := -march=armv7e-m
+  # FIXME: Most tools do not yet fpv5 FPU types either
   ifeq ($(CONFIG_ARCH_FPU),y)
-    # TOOLCHAIN_MFLOAT := -mfpu=fpv5-sp-d16 -mfloat-abi=hard # Single precision
+  ifeq ($(CONFIG_ARCH_DPFPU),y)
     TOOLCHAIN_MFLOAT := -mfpu=fpv5-d16 -mfloat-abi=hard
+  else
+    TOOLCHAIN_MFLOAT := -mfpu=fpv5-sp-d16 -mfloat-abi=hard
+  endif
   else
     TOOLCHAIN_MFLOAT := -mfloat-abi=soft
   endif

arch/arm/src/samv7/Kconfig

@@ -54,8 +54,12 @@ endchoice # Atmel SAMV7 Chip Selection
 config ARCH_CHIP_SAMV71
 	bool
 	default n
+	select ARCH_HAVE_FPU
+	select ARCH_HAVE_DPFPU # REVISIT
 	select ARMV7M_HAVE_ICACHE
 	select ARMV7M_HAVE_DCACHE
+	select ARMV7M_HAVE_ITCM
+	select ARMV7M_HAVE_DTCM
 
 config ARCH_CHIP_SAMV71Q
 	bool

configs/samv71-xult/nsh/defconfig

@@ -110,7 +110,9 @@ CONFIG_ARCH_CHIP="samv7"
 CONFIG_ARCH_HAVE_CMNVECTOR=y
 CONFIG_ARMV7M_CMNVECTOR=y
 # CONFIG_ARMV7M_LAZYFPU is not set
-# CONFIG_ARCH_HAVE_FPU is not set
+CONFIG_ARCH_HAVE_FPU=y
+CONFIG_ARCH_HAVE_DPFPU=y
+# CONFIG_ARCH_FPU is not set
 # CONFIG_ARMV7M_MPU is not set
 
 #
@@ -120,6 +122,10 @@ CONFIG_ARMV7M_HAVE_ICACHE=y
 CONFIG_ARMV7M_HAVE_DCACHE=y
 # CONFIG_ARMV7M_ICACHE is not set
 # CONFIG_ARMV7M_DCACHE is not set
+CONFIG_ARMV7M_HAVE_ITCM=y
+CONFIG_ARMV7M_HAVE_DTCM=y
+# CONFIG_ARMV7M_ITCM is not set
+# CONFIG_ARMV7M_DTCM is not set
 # CONFIG_ARMV7M_TOOLCHAIN_ATOLLIC is not set
 # CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT is not set
 # CONFIG_ARMV7M_TOOLCHAIN_CODEREDW is not set

configs/samv71-xult/scripts/flash.ld

@@ -34,11 +34,14 @@
  ****************************************************************************/
 
 /* The SAMV71Q21 has 2048Kb of FLASH beginning at address 0x0400:0000 and
- * 384Kb of SRAM beginining at 0x2000:0000
+ * 384Kb of SRAM beginining at 0x2040:0000
  *
  * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000
  * where the code expects to begin execution by jumping to the entry point in
- * the 0x0800:0000 address range.
+ * the 0x0400:0000 address range (Assuming that ITCM is not enable).
+ *
+ * NOTE: that the DTCM address of 0x2000:0000 is used for SRAM.  If DTCM is
+ * disabled, then the accesses will actually occur on the AHB bus.
  */
 
 MEMORY

configs/samv71-xult/scripts/memory.ld

@@ -34,11 +34,14 @@
  ****************************************************************************/
 
 /* The SAMV71Q21 has 2048Kb of FLASH beginning at address 0x0400:0000 and
- * 384Kb of SRAM beginining at 0x2000:0000
+ * 384Kb of SRAM beginining at 0x2040:0000
  *
  * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000
  * where the code expects to begin execution by jumping to the entry point in
- * the 0x0800:0000 address range.
+ * the 0x0400:0000 address range.
+ *
+ * NOTE: that the DTCM address of 0x2000:0000 is used for SRAM.  If DTCM is
+ * disabled, then the accesses will actually occur on the AHB bus.
  *
  * The user space partition will be spanned with a single region of size
  * 2**n bytes.  The alignment of the user-space region must be the same.