Correct some typos in STM32 RCC header files noted by Ramtin Amin

arch/arm/src/stm32/chip/stm32f10xxx_rcc.h

@@ -209,8 +209,8 @@
 #define RCC_APB2RSTR_IOPCRST        (1 << 4)  /* Bit 4: IO port C reset */
 #define RCC_APB2RSTR_IOPDRST        (1 << 5)  /* Bit 5: IO port D reset */
 #define RCC_APB2RSTR_IOPERST        (1 << 6)  /* Bit 6: IO port E reset */
-#define TCC_APB2RSTR_IOPFRST        (1 << 7)  /* Bit 7: IO port F reset */
-#define TCC_APB2RSTR_IOPGRST        (1 << 8)  /* Bit 8: IO port G reset */
+#define RCC_APB2RSTR_IOPFRST        (1 << 7)  /* Bit 7: IO port F reset */
+#define RCC_APB2RSTR_IOPGRST        (1 << 8)  /* Bit 8: IO port G reset */
 #define RCC_APB2RSTR_ADC1RST        (1 << 9)  /* Bit 9: ADC 1 interface reset */
 #ifndef CONFIG_STM32_VALUELINE
 #  define RCC_APB2RSTR_ADC2RST      (1 << 10) /* Bit 10: ADC 2 interface reset */

arch/arm/src/stm32/chip/stm32f20xxx_rcc.h

@@ -184,7 +184,7 @@
 #  define RCC_CFGR_MCO1_LSE         (1 << RCC_CFGR_MCO1_SHIFT) /* 01: LSE oscillator selected */
 #  define RCC_CFGR_MCO1_HSE         (2 << RCC_CFGR_MCO1_SHIFT) /* 10: HSE oscillator clock selected */
 #  define RCC_CFGR_MCO1_PLL         (3 << RCC_CFGR_MCO1_SHIFT) /* 11: PLL clock selected */
-#define TCC_CFGR_I2SSRC             (1 << 23) /* Bit 23: I2S clock selection */
+#define RCC_CFGR_I2SSRC             (1 << 23) /* Bit 23: I2S clock selection */
 #define RCC_CFGR_MCO1PRE_SHIFT      (24)      /* Bits 24-26: MCO1 prescaler */
 #define RCC_CFGR_MCO1PRE_MASK       (7 << RCC_CFGR_MCO1PRE_SHIFT)
 #  define RCC_CFGR_MCO1PRE_NONE     (0 << RCC_CFGR_MCO1PRE_SHIFT) /* 0xx: no division */

arch/arm/src/stm32/chip/stm32f40xxx_rcc.h

@@ -194,7 +194,7 @@
 #  define RCC_CFGR_MCO1_LSE         (1 << RCC_CFGR_MCO1_SHIFT) /* 01: LSE oscillator selected */
 #  define RCC_CFGR_MCO1_HSE         (2 << RCC_CFGR_MCO1_SHIFT) /* 10: HSE oscillator clock selected */
 #  define RCC_CFGR_MCO1_PLL         (3 << RCC_CFGR_MCO1_SHIFT) /* 11: PLL clock selected */
-#define TCC_CFGR_I2SSRC             (1 << 23) /* Bit 23: I2S clock selection */
+#define RCC_CFGR_I2SSRC             (1 << 23) /* Bit 23: I2S clock selection */
 #define RCC_CFGR_MCO1PRE_SHIFT      (24)      /* Bits 24-26: MCO1 prescaler */
 #define RCC_CFGR_MCO1PRE_MASK       (7 << RCC_CFGR_MCO1PRE_SHIFT)
 #  define RCC_CFGR_MCO1PRE_NONE     (0 << RCC_CFGR_MCO1PRE_SHIFT) /* 0xx: no division */