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Commit 5a7b2757 authored by Gregory Nutt's avatar Gregory Nutt
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Add definitions for SMSC LAN8742A PHY

parent 9c9c31ec
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......@@ -349,6 +349,9 @@ config ETH0_PHY_LAN8740
config ETH0_PHY_LAN8740A
bool "SMSC LAN8740A PHY"
config ETH0_PHY_LAN8742A
bool "SMSC LAN8742A PHY"
config ETH0_PHY_DM9161
bool "Davicom DM9161 PHY"
......
......@@ -169,7 +169,7 @@
#define MII_LAN8720_IMR 0x1e /* Interrupt Mask Register */
#define MII_LAN8720_SCSR 0x1f /* PHY Special Control/Status Register */
/* SMSC LAN8740 PHY Extended Registers */
/* SMSC LAN8740/LAN8742A PHY Extended Registers */
#define MII_LAN8740_CONFIG 0x10 /* EDPD NDL/Crossover Timer/EEE Configuration */
#define MII_LAN8740_MCSR 0x11 /* Mode Control/Status Register */
......@@ -361,6 +361,11 @@
#define MII_PHYID1_LAN8740A 0x0007 /* ID1 value for LAN8740A */
#define MII_PHYID2_LAN8740A 0xc111 /* ID2 value for LAN8740A */
/* SMSC LAN8742A MII ID1/2 register bits */
#define MII_PHYID1_LAN8742A 0x0007 /* ID1 value for LAN8742A */
#define MII_PHYID2_LAN8742A 0xc130 /* ID2 value for LAN8742A */
/* Am79c874-specific register bit settings **********************************/
/* Am79c874 MII ID1/2 register bits */
......
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