STM32 SPI: The source clock for SPI 4,5, and 6 should be PCLK2, not PCLK1...

STM32 SPI:  The source clock for SPI 4,5, and 6 should be PCLK2, not PCLK1 (for F411, F427, and F429).  Per David Sidrane.

arch/arm/src/stm32/stm32_spi.c

@@ -409,7 +409,7 @@ static struct stm32_spidev_s g_spi4dev =
 {
   .spidev   = { &g_sp4iops },
   .spibase  = STM32_SPI4_BASE,
-  .spiclock = STM32_PCLK1_FREQUENCY,
+  .spiclock = STM32_PCLK2_FREQUENCY,
 #ifdef CONFIG_STM32_SPI_INTERRUPTS
   .spiirq   = STM32_IRQ_SPI4,
 #endif
@@ -448,7 +448,7 @@ static struct stm32_spidev_s g_spi5dev =
 {
   .spidev   = { &g_sp5iops },
   .spibase  = STM32_SPI5_BASE,
-  .spiclock = STM32_PCLK1_FREQUENCY,
+  .spiclock = STM32_PCLK2_FREQUENCY,
 #ifdef CONFIG_STM32_SPI_INTERRUPTS
   .spiirq   = STM32_IRQ_SPI5,
 #endif
@@ -487,7 +487,7 @@ static struct stm32_spidev_s g_spi6dev =
 {
   .spidev   = { &g_sp6iops },
   .spibase  = STM32_SPI6_BASE,
-  .spiclock = STM32_PCLK1_FREQUENCY,
+  .spiclock = STM32_PCLK2_FREQUENCY,
 #ifdef CONFIG_STM32_SPI_INTERRUPTS
   .spiirq   = STM32_IRQ_SPI6,
 #endif

drivers/serial/lowconsole.c

@@ -115,6 +115,7 @@ static ssize_t lowconsole_write(struct file *filep, const char *buffer, size_t b
     {
       up_putc(*buffer++);
     }
+
   return ret;
 }