Add eZ80 I2C driver

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@1679 42af7a65-404d-4744-a932-0658087f49c3

arch/z80/src/ez80/Make.defs

 ############################################################################
 # arch/z80/src/ez80/Make.defs
 #
-#   Copyright (C) 2008, 2009 Gregory Nutt. All rights reserved.
+#   Copyright (C) 2008-2009 Gregory Nutt. All rights reserved.
 #   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
 #
 # Redistribution and use in source and binary forms, with or without
@@ -52,7 +52,8 @@ endif
 CHIP_SSRCS	= 
 CHIP_CSRCS	= ez80_clock.c ez80_initialstate.c ez80_irq.c ez80_copystate.c \
 		  ez80_schedulesigaction.c ez80_sigdeliver.c ez80_timerisr.c \
-		  ez80_lowuart.c ez80_serial.c ez80_spi.c ez80_registerdump.c
+		  ez80_lowuart.c ez80_serial.c ez80_spi.c ez80_i2c.c \
+		  ez80_registerdump.c
 ifeq ($(CONFIG_ARCH_CHIP_EZ80F91),y)
 ifeq ($(CONFIG_EZ80_EMAC),y)
 CHIP_CSRCS	+= ez80_emac.c

arch/z80/src/ez80/ez80f91_i2c.h

@@ -80,12 +80,43 @@
 #define I2C_SR_SHIFT     3        /* Bits 3-7: 5-bit status code */
 #define I2C_SR_MASK      (0x1c << I2C_SR_SHIFT)
 
+
+#define I2C_SR_BUSERR      0x00 /* Bus error */
+#define I2C_SR_MSTART      0x08 /* START condition transmitted */
+#define I2C_SR_MREPSTART   0x10 /* Repeated START condition transmitted */
+#define I2C_SR_MADDRWRACK  0x18 /* Address and Write bit transmitted, ACK received */
+#define I2C_SR_MADDRWR     0x20 /* Address and Write bit transmitted, ACK not received */
+#define I2C_SR_MDATAWRACK  0x28 /* Data byte transmitted in MASTER mode, ACK received */
+#define I2C_SR_MDATAWR     0x30 /* Data byte transmitted in MASTER mode, ACK not received */
+#define I2C_SR_ARBLOST1    0x38 /* Arbitration lost in address or data byte */
+#define I2C_SR_MADDRRDACK  0x40 /* Address and Read bit transmitted, ACK received */
+#define I2C_SR_MADDRRD     0x48 /* Address and Read bit transmitted, ACK not received */
+#define I2C_SR_MDATARDACK  0x50 /* Data byte received in MASTER mode, ACK transmitted */
+#define I2C_SR_MDATARDNAK  0x58 /* Data byte received in MASTER mode, NACK transmitted */
+#define I2C_SR_SADDRWRACK  0x60 /* Slave address and Write bit received, ACK transmitted */
+#define I2C_SR_ARBLOST2    0x68 /* Arbitration lost in address as master, slave address and Write bit received, ACK transmitted */
+#define I2C_SR_SGCARDACK   0x70 /* General Call address received, ACK transmitted */
+#define I2C_SR_ARBLOST3    0x78 /* Arbitration lost in address as master, General Call address received, ACK transmitted */
+#define I2C_SR_SDATARDACK  0x80 /* Data byte received after slave address received, ACK transmitted */
+#define I2C_SR_SDATARDNAK  0x88 /* Data byte received after slave address received, NACK transmitted */
+#define I2C_SR_SDATAGCAACK 0x90 /* Data byte received after General Call received, ACK transmitted */
+#define I2C_SR_SDATAGCANAK 0x98 /* Data byte received after General Call received, NACK transmitted */
+#define I2C_SR_SSTOP       0xa0 /* STOP or repeated START condition received in SLAVE mode */
+#define I2C_SR_SSADDRRDACK 0xa8 /* Slave address and Read bit received, ACK transmitted */
+#define I2C_SR_ARBLOST4    0xb0 /* Arbitration lost in address as master, slave address and Read bit received, ACK transmitted */
+#define I2C_SR_SDATAWRACK  0xb8 /* Data byte transmitted in SLAVE mode, ACK received */
+#define I2C_SR_SDATAWR     0xc0 /* Data byte transmitted in SLAVE mode, ACK not received */
+#define I2C_SR_SLDATAWR    0xc8 /* Last byte transmitted in SLAVE mode, ACK received */
+#define I2C_SR_MADDR2WRACK 0xd0 /* Second Address byte and Write bit transmitted, ACK received */
+#define I2C_SR_MADDR2WR    0xd8 /* Second Address byte and Write bit transmitted, ACK not received */
+#define I2C_SR_NONE        0xf8 /* No relevant status information, IFLG = 0 */
+
 /* Clock Control Register (CCR) Bit Definitions */
 
 #define I2C_CCR_NSHIFT   0        /* Bits 0-2: I2C clock divider exponent */
 #define I2C_CCR_NMASK    (0x07 << I2C_CCR_NSHIFT)
 #define I2C_CCR_MSHIFT   3        /* Bits 3-6: I2C clock divider scalar value */
-#define I2C_CCR_NMASK    (0x0f << I2C_CCR_MSHIFT)
+#define I2C_CCR_MMASK    (0x0f << I2C_CCR_MSHIFT)
 
 /* Software Reset Register (SRR) Bit Definitions */
 /* Writing any value to this register performs a software reset of the I2C module */

include/nuttx/i2c.h

@@ -47,10 +47,28 @@
  * Definitions
  ****************************************************************************/
 
-/* I2C address calculation.  Convert 7-bit address to 8-bit read/write address */
+/* I2C address calculation.  Convert 7- and 10-bit address to 8-bit and
+ * 16-bit read/write address
+ */
+
+#define I2C_READBIT          0x01
+
+/* Conver 7- to 8-bit address */
+
+#define I2C_ADDR8(a)         ((a) << 1)
+#define I2C_WRITEADDR8(a)    I2C_ADDR8(a)
+#define I2C_READADDR8(a)     (I2C_ADDR8(a) | I2C_READBIT)
+
+/* Convert 10- to 16-bit address */
+
+#define I2C_ADDR10H(a)       (0xf0 | (((a) >> 7) & 0x06))
+#define I2C_ADDR10L(a)       ((a) & 0xff)
+
+#define I2C_WRITEADDR10H(a)  I2C_ADDR10H(a)
+#define I2C_WRITEADDR10L(a)  I2C_ADDR10L(a)
 
-#define I2C_READADDR(a)  (((a) << 1) | 1)
-#define I2C_WRITEADDR(a)  ((a) << 1)
+#define I2C_READADDR10H(a)   (I2C_ADDR10H(a) | I2C_READBIT)
+#define I2C_READADDR10L(a)   I2C_ADDR10L(a)
 
 /* Access macros */
 
@@ -82,13 +100,14 @@
  * Input Parameters:
  *   dev -     Device-specific state data
  *   address - The I2C slave address
+ *   nbits -   The number of address bits provided (7 or 10)
  *
  * Returned Value:
  *   Returns the actual frequency selected
  *
  ****************************************************************************/
 
-#define I2C_SETADDRESS(d,f) ((d)->ops->setaddress(d,f))
+#define I2C_SETADDRESS(d,f,b) ((d)->ops->setaddress(d,f,b))
 
 /****************************************************************************
  * Name: I2C_WRITE
@@ -142,7 +161,7 @@ struct i2c_dev_s;
 struct i2c_ops_s
 {
   uint32 (*setfrequency)(FAR struct i2c_dev_s *dev, uint32 frequency);
-  int    (*setaddress)(FAR struct i2c_dev_s *dev, int addr);
+  int    (*setaddress)(FAR struct i2c_dev_s *dev, int addr, int nbits);
   int    (*write)(FAR struct i2c_dev_s *dev, const ubyte *buffer, int buflen);
   int    (*read)(FAR struct i2c_dev_s *dev, ubyte *buffer, int buflen);
 };